AD9265 Analog Devices, AD9265 Datasheet - Page 29

• Manufacturer Part Number: AD9265
• Description: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9265

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 57). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9265 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias.
Clock Input Options
The AD9265 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9265. A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
–0.5
–1.0
–1.5
–2.0
CLK+
2.0
1.5
1.0
0.5
0
–40
Figure 73. Typical VREF Drift Update Figure
Figure 74. Equivalent Clock Input Circuit
–20
4pF
VREF = 1.0V
0
TEMPERATURE (°C)
AVDD
0.9V
20
40
60
4pF
CLK–
80
Rev. A | Page 29 of 44
The RF balun configuration is recommended for clock frequencies
at 625 MHz and the RF transformer is recommended for clock
frequencies from 10 MHz to 200 MHz. The back-to-back Schottky
diodes across the transformer/balun secondary limit clock excur-
sions into the AD9265 to approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9265 while
preserving the fast rise and fall times of the signal that are critical
to low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/
AD9522
CLOCK
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522 clock drivers offer excellent jitter
performance.
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
Figure 77. Differential PECL Sample Clock (Up To Rated Sample Rate)
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
50kΩ
clock drivers offer excellent jitter performance.
Figure 76. Balun-Coupled Differential Clock (625 MHz)
50Ω
0.1µF
50Ω
1nF
0.1µF
0.1µF
50kΩ
1nF
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
AD95xx
PECL DRIVER
XFMR
0.1µF
240Ω
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
240Ω
0.1µF
0.1µF
100Ω
CLK+
CLK–
AD9265
CLK+
CLK–
CLK+
CLK–
AD9265
ADC
AD9265
AD9265
ADC
ADC