AD9255 Analog Devices, AD9255 Datasheet - Page 40

• Manufacturer Part Number: AD9255
• Description: 14-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9255

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 125MSPS
• Interface: LVDS,Par,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9255
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9255 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9255, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs (DRVDD).
Several different decoupling capacitors can be used to cover both
high and low frequencies. Locate these capacitors close to the
point of entry at the PCB level and close to the pins of the part,
with minimal trace length. The power supply for the SPI port,
SVDD, should not contain excessive noise and should also be
bypassed close to the part.
A single PCB ground plane should be sufficient when using the
AD9255. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
The AD9255 can be configured for CMOS or LVDS output mode
on power-up using the LVDS pin, Pin 44. If LVDS operation is
desired, connect Pin 44 to AVDD. LVDS operation can also be
enabled through the SPI port. If CMOS operation is desired,
connect Pin 44 to AGND.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to the analog ground (AGND) to achieve
the best electrical and thermal performance. A continuous,
exposed (no solder mask) copper plane on the PCB should mate
to the AD9255 exposed paddle, Pin 0. The copper plane
Rev. A | Page 40 of 44
should have several vias to achieve the lowest possible resistive
thermal path for heat dissipation to flow through the bottom of
the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only one
tie point between the ADC and the PCB. For detailed information
about packaging and PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide for
the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
VCM
Decouple the VCM pin to ground with a 0.1 μF capacitor, as
shown in Figure 67.
RBIAS
The AD9255 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
Decouple the VREF pin externally to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter per-
formance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9255 to keep these signals from transitioning at the converter
inputs during critical sampling periods.