AD7171 Analog Devices, AD7171 Datasheet - Page 5

• Manufacturer Part Number: AD7171
• Description: 16-Bit Low Power ??? ADC
• Manufacturer: Analog Devices

Specifications of AD7171

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

TIMING CHARACTERISTICS
V
Table 2.
Parameter
READ
RESET
1
2
3
4
TIMING DIAGRAMS
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3.
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
SCLK active edge is the falling edge of SCLK.
DD
t
t
t
t
t
t
1
2
3
4
5
6
3
= 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V
1, 2
Limit at T
100
100
0
60
80
10
100
25
MIN
DOUT/RDY (O)
, T
MAX
SCLK (I)
DOUT/RDY (O)
OUTPUT
PDRST (I)
I = INPUT, O = OUTPUT
Figure 2. Load Circuit for Timing Characterization
PIN
TO
I = INPUT, O = OUTPUT
50pF
Figure 3. Read Cycle Timing Diagram
Figure 4. Resetting the AD7171
t
5
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MSB
t
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ms typ
3
I
100µA WITH V
I
100µA WITH V
SINK
SOURCE
t
1
(1.6mA WITH V
t
6
(200µA WITH V
t
DD
2
1.6V
, unless otherwise noted.
DD
DD
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay
V
V
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
PDRST high to data valid delay
R
= 3V)
= 3V)
DD
DD
= t
DD
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
F
t
= 5 ns (10% to 90% of V
4
LSB
= 5V,
DD
= 5V,
DD
) and timed from a voltage level of 1.6 V.
OL
or V
OH
4
limits.
AD7171