AD7606 Analog Devices, AD7606 Datasheet - Page 9

• Manufacturer Part Number: AD7606
• Description: 8-Channel DAS with 16-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7606

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

Data Sheet
Parameter
1
2
3
4
Timing Diagrams
Sample tested during initial release to ensure compliance. All input signals are specified with t
In oversampling mode, typical t
t
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
CONV
t
t
t
27
28
29
= 3 µs; and for the AD7606-4, t
CONVST A,
CONVST A,
CONVST A,
CONVST A,
CONVST B
CONVST B
CONVST B
CONVST B
RESET
RESET
BUSY
BUSY
CS
CS
CONV
for the AD7606-6 and AD7606-4 can be calculated using ((N × t
CONV
Min
= 2 µs.
Logic Input Levels)
Limit at T
(0.1 × V
0.9 × V
t
t
t
Typ
1
7
7
DRIVE
t
t
RESET
RESET
MIN
t
t
DRIVE
Figure 3. CONVST Timing—Reading During a Conversion
5
5
Figure 2. CONVST Timing—Reading After a Conversion
, T
and
MAX
Max
19
24
17
22
24
t
1
Min
Logic Input Levels)
Limit at T
(0.3 × V
Rev. C | Page 9 of 36
0.7 × V
Typ
DRIVE
MIN
DRIVE
, T
and
MAX
Max
22
29
20
27
29
t
t
t
t
CYCLE
CYCLE
CONV
CONV
t
t
3
3
R
= t
CONV
Unit
ns
ns
ns
ns
ns
F
= 5 ns (10% to 90% of V
) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6,
t
6
Description
Delay from RD falling edge to FRSTDATA low
V
V
Delay from 16
V
V
Delay from CS rising edge until FRSTDATA three-
state enabled
DRIVE
DRIVE
DRIVE
DRIVE
AD7606/AD7606-6/AD7606-4
= 3.3 V to 5.25V
= 2.3 V to 2.7V
= 3.3 V to 5.25V
= 2.3 V to 2.7V
t
4
DRIVE
th
SCLK falling edge to FRSTDATA low
) and timed from a voltage level of 1.6 V.
t
t
2
2