AD6672 Analog Devices, AD6672 Datasheet - Page 26

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6672
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Transfer Register
0xFF
ADC Functions Registers
0x08
0x09
0x0B
0x0D
0x0E
Register
Name
SPI port
configuration
Chip ID
Chip grade
Transfer
Power modes
Global clock
Clock divide
Test mode
BIST enable
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
User test
mode
control
0 = con-
tinuous/
repeat
pattern
1 =
single
pattern,
then 0s
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
Open
Reset PN
long gen
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Speed grade ID
00 = 250 MSPS
Bit 4
1
Open
Open
Open
Reset PN
short gen
Open
Rev. 0 | Page 26 of 32
(AD6672
8-bit chip ID[7:0]
(default)
= 0xA4)
Bit 3
1
Open
Open
Open
Open
Open
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
Bit 2
Soft reset
Open
Open
Open
Open
Reset BIST
sequence
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Clock divide ratio
000 = divide by 1
Bit 1
LSB first
Open
Open
Internal power-down
mode
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Open
Open
Bit 0
(LSB)
0
Open
Transfer
Duty
cycle
stabilizer
(default)
BIST
enable
Default
Value
(Hex)
0x18
0xA4
0x00
0x00
0x01
0x00
0x00
0x00
Default
Notes/
Comments
Nibbles are
mirrored so
that LSB
first mode
or MSB first
mode is set
correctly,
regardless
of shift
mode.
Read only.
Speed
grade ID
used to dif-
ferentiate
devices;
read only.
Synchro-
nously
transfers
data from
the master
shift
register to
the slave.
Determines
various
generic
modes
of chip
operation.
Clock
divide
values
other than
000 auto-
matically
cause the
duty cycle
stabilizer
to become
active.
When this
register is
set, the
test data is
placed on
the output
pins in
place of
normal
data.