SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 198

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

AC and DC Parameters
7.22
7-26
Address latch enable control
Figure 7-22 shows the ARM7TDMI reset period timing. The timing parameters used in
Figure 7-22 are listed in Table 7-21.
In Figure 7-22, T
address in phase 2. If ALE is driven LOW after T
is known as address breakthrough.
Note
Copyright © 1994-2001. All rights reserved.
MAS[1:0]
nTRANS
ald
A[31:0]
MCLK
LOCK
nOPC
is the time by which ALE must be driven LOW to latch the current
nRW
ALE
Symbol
T
T
T
ald
ale
aleh
Table 7-21 ALE address control timing parameters
Parameter
Address group latch output time
Address group latch open output delay
Address group latch output hold time
Phase 1
T
ale
ald
, then a new address is latched. This
T
aleh
Figure 7-22 ALE control timing
T
ald
Phase 2
ARM DDI 0029G
Maximum
Maximum
Minimum
Parameter
type