SAM7X128 Atmel Corporation, SAM7X128 Datasheet

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... Bytes (Dual Plane) – 256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • Single Cycle Access MHz in Worst Case Conditions • Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed • ...

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Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator • Two Parallel Input/Output Controllers (PIO) – Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability ...

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... Ethernet, CAN wired and Zigbee networks. 1.1 Configuration Summary of the SAM7X512/256/128 The SAM7X512, SAM7X256 and SAM7X128 differ only in memory sizes. the configurations of the three devices. Table 1-1. Device SAM7X512 ...

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SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF SAM7X512/256/128 Summary 4 SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK ...

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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL ...

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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...

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Table 3-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK ...

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Package The SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-com- pliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. SAM7X512/256/128 Summary 8 shows the orientation of ...

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LQFP Pinout Table 4-1. Pinout in 100-lead LQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT 32 8 VDDIN 33 9 PB27/AD0 34 10 PB28/AD1 ...

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TFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 4.4 100-ball TFBGA Pinout Pinout in 100-ball TFBGA Package Pin Signal Name Pin A1 PA22/PGMD10 C6 A2 PA21/PGMD9 C7 ...

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Power Considerations 5.1 Power Supplies The SAM7X512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. ...

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Typical Powering Schematics The SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. the power schematics to be used for USB bus-powered systems. ...

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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, ...

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PIO Controller Lines All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma- ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO ...

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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM high-performance 32-bit instruction set – Thumb high code ...

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Embedded Flash Controller – Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and ...

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... Protection Mode to secure contents of the Flash • 64 Kbytes of Fast SRAM – Single-cycle access at full speed 8.3 SAM7X128 • 128 Kbytes of Flash Memory – 512 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...

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Figure 8-1. SAM7X512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF SAM7X512/256/128 Summary 18 Internal ...

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... The SAM7X512 features two banks (dual plane) of 256 Kbytes of Flash. • The SAM7X256 features one bank (single plane) of 256 Kbytes of Flash. • The SAM7X128 features one bank (single plane) of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset, if GPNVM bit 2 is set and before the Remap Command ...

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... The Flash of the SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. • The Flash of the SAM7X128 is organized in 512 pages of 256 bytes (single plane). It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. ...

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... SAM7X128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7X128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command “ ...

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When the security bit is deactivated, all accesses to the flash are permitted important to note that the assertion of the ERASE pin should always be longer than 220 ms. As ...

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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...

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Figure 9-1. NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 SAM7X512/256/128 Summary 24 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset ...

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Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin ...

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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 ...

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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable ...

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... Chip ID is 0x275C 0A40 (MRL A) for SAM7X512 – Chip ID is 0x275B 0940 (MRL for SAM7X256 – Chip ID is 0x275B 0942 (MRL C) for SAM7X256 – Chip ID is 0x275A 0740 (MRL for SAM7X128 – Chip ID is 0x275A 0742 (MRL C) for SAM7X128 9.6 Periodic Interval Timer • ...

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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SLCK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • ...

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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...

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Peripheral Multiplexing on PIO Lines The SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral ...

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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 PA9 CTS1 PA10 ...

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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 ETXCK/EREFCK PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ...

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Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • ...

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One, two or three bytes internal address registers for easy Serial Memory access • 7-bit or 10-bit slave addressing • Sequential read/write operations 10.9 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial ...

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Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4. TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 ...

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CAN Controller • Fully compliant with CAN 2.0A and 2.0B • Bit rates up to 1Mbit/s • Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B Programmable for each ...

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Package Drawings Figure 11-1. LQFP Package Drawing SAM7X512/256/128 Summary 38 6120GS–ATARM–07-Apr-11 ...

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Table 11-1. Symbol θ1 θ2 θ aaa bbb ccc ddd 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary 100-lead LQFP Package Dimensions Millimeter Min Nom Max 1.60 ...

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Figure 11-2. TFBGA Package Drawing All dimensions are in mm SAM7X512/256/128 Summary 40 6120GS–ATARM–07-Apr-11 ...

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... AT91SAM7X256-CU AT91SAM7X256B-CU AT91SAM7X128-AU AT91SAM7X128B-AU AT91SAM7X128-CU AT91SAM7X128B-CU 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary MLR C Ordering Code – AT91SAM7X256C-AU AT91SAM7X256C-CU AT91SAM7X128C-AU AT91SAM7X128C-CU Package Package Type Operating Range LQFP 100 Green (-40⋅ 85⋅ C) TFBGA 100 LQFP 100 Green (-40⋅ 85⋅ C) TFBGA 100 ...

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Revision History Table 12-2. Revision History Doc. Rev Comments 6120AS First issue - Unqualified on Intranet Legal page updated.Qualified on Intranet 6120BS Corrections to maintain consistency with full datasheet: In “Features” on page PDC channels, removed Wake-on-LAN support. In Figure ...

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Table 12-2. Revision History Doc. Rev Comments 6120ES “Features”,TWI updated to include Atmel TWI compatibility with I2C Standard. Section 10.8 ”Two-wire Section 7.4 ”Peripheral DMA Section 10.11 ”Timer Section 10.15 ”Analog-to-Digital 6120FS Table 3-1, “Signal Description List” Section 6.1 ”JTAG ...

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