SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet - Page 79

• Manufacturer Part Number: SAM7SE512
• Manufacturer: Atmel Corporation

Specifications of SAM7SE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3.5
ARM DDI 0029G
Coprocessor register transfer cycles
When designing a memory controller, ensure that the design also works when an I-cycle
is followed by an N-cycle to a different address. This sequence can occur during
exceptions, or during writes to the PC. It is essential that the memory controller does
not commit to the memory cycle during an I-cycle.
During a coprocessor register transfer cycle, the ARM7TDMI processor uses the data
buses to transfer data to or from a coprocessor. A memory cycle is not required and the
memory controller does not initiate a transaction. The memory system must not drive
onto the data bus during a coprocessor register transfer cycle.
The coprocessor interface is described in Chapter 4 Coprocessor Interface. The
coprocessor register transfer cycle is shown in Figure 3-6 on page 3-10.
Note
Copyright © 1994-2001. All rights reserved.
nMREQ
A[31:0]
D[31:0]
MCLK
nRAS
nCAS
SEQ
I-cycle
Figure 3-5 Merged IS cycle
S-cycle
Memory Interface
3-9