SAM3S2C Atmel Corporation, SAM3S2C Datasheet - Page 49

• Manufacturer Part Number: SAM3S2C
• Manufacturer: Atmel Corporation

Specifications of SAM3S2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.7
6500CS–ATARM–24-Jan-11
Pulse Width Modulation Controller (PWM)
• Each channel is user-configurable and contains:
• Two global registers that act on all three TC Channels
• Quadrature decoder
• 2-bit Gray Up/Down Counter for Stepper Motor
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
• Independent channel programming
• Synchronous Channel mode
• Connection to one PDC channel
• independent event lines which can send up to 4 triggers on ADC within a period
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– Advanced line filtering
– Position / revolution / speed
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
– Offers Buffer transfer without Processor Intervention, to update duty cycle of
channel
of periods
synchronous channels
SAM3S Summary
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