ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 252

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.14 Register Description
20.14.1
8331A–AVR–07/11
STATUS – Endpoint Status Register
Bit
+0x00
Read/Write
Initial Value
Each of the 16 endpoint addresses have one input and one output endpoint. Each endpoint has
8 bytes of configuration/status data located in internal SRAM.
The address to the first configuration byte is (EPPTR[15:0] + 16 * endpoint address) for output
endpoints and (EPPTR[15:0] + 16 * endpoint address + 8) for input endpoints.
Some bit locations have different functions depending on endpoint configuration type or direc-
tion, and this is reflected by using two different names for the bit locations.
Note:
• Bit 7 – STALL: Endpoint Stall Flag
This flag is set when an IN or OUT transaction has been responded to with a STALL handshake.
This flag is cleared by writing a one to its bit location.
• Bit 7 – CRC: CRC Error Flag
This flag is set for isochronous output endpoints when a CRC error has been detected in an
incoming data packet. This flag is cleared by writing a one to its bit location.
• Bit 6 – UNF/OVF: Underflow / Overflow Flag
UNF:
OVF:
• Bit 5 – TRNCOMPL0: Transaction Complete Flag
This flag is set when an IN or OUT transaction has completed successfully. This flag is cleared
by writing a one to its bit location.
• Bit 4 – SETUP: SETUP Transaction Complete Flag
This flag is set when a SETUP transaction has completed successfully or an IN or OUT transac-
tion has completed successfully. This flag is cleared by writing a one to its bit location.
• Bit 4 – TRNCOMPL1: Transaction Complete Flag
This flag is set when a SETUP transaction has completed successfully or an IN or OUT transac-
tion has completed successfully. This flag is cleared by writing a one to its bit location.
1. For isochronous endpoints
For output endpoints, the OVF flag is set when an output endpoint is not ready to
data to the host in response of an IN token.
accept data from the host following an OUT token.
For input endpoints, the UNF flag is set when an input endpoint is not ready to send
–
STALL
CRC
R/W
USB Endpoint
7
0
(1)
UNF/ OVF
R/W
6
0
TRNCOMPL0
R/W
5
0
TRNCOMPL1
SETUP
R/W
4
0
BANK
R/W
Atmel AVR XMEGA AU
3
0
BUSNACK1
R/W
2
0
BUSNACK0
R/W
1
0
TOGGLE
R/W
0
0
STATUS
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