ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 137

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ATxmega256A3

Manufacturer Part Number
ATxmega256A3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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13.10 Slew-rate Control
13.11 Clock and Event Output
8077H–AVR–12/09
Figure 13-10. Port override signals and related logic
Slew-rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will
typically increase the rise/fall time by 50-150% depending on voltage, temperature and load. For
information about the characteristics of the slew-rate limiter, please refer to the device data
sheet.
It is possible to output both the Peripheral Clock and the signaling event from Event Channel 0
to pin. Output port pin is selected from software. If an event occur on Event Channel 0, this will
PINnCTRL
D
D
D
Q
OUTn
DIRn
INn
R
R
R
R
Synchronizer
Analog Input/Output
Q
Q
Q
D
Digital Input Pin
Q
OUT Override Value
OUT Override Enable
R
DIR Override Value
DIR Override Enable
D
Pull Enable
Pull Keep
Pull Direction
Digital Input Disable (DID)
Wired AND/OR
Slew Rate Limit
Inverted I/O
DID Override Value
DID Override Enable
XMEGA A
Pxn
137

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