ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 24

• Manufacturer Part Number: ATxmega192D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega192D3

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13. PMIC - Programmable Multi-level Interrupt Controller
13.1
13.2
13.3
Table 13-1.
8134I–AVR–12/10
Program Address
(Base Address)
Features
Overview
Interrupt vectors
0x01C
0x000
0x002
0x004
0x008
0x014
0x018
0x028
0x030
0x032
0x040
0x044
0x056
Reset and Interrupt Vectors
Source
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
NVM_INT_base
PORTB_INT_base
PORTE_INT_base
•
•
•
•
XMEGA D3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA D3 devices are
shown in
described for each peripheral in the XMEGA A manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in
address.
Separate interrupt vector for each interrupt
Short, predictable interrupt response time
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved to the start of the Boot Section
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
Table
13-1. Offset addresses for each interrupt available in the peripheral are
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E INT base
Table
13-1. The program address is the word
XMEGA D3
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