ATmega3250 Atmel Corporation, ATmega3250 Datasheet - Page 32
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ATmega3250
Manufacturer Part Number
ATmega3250
Description
Manufacturer
Atmel Corporation
Specifications of ATmega3250
Flash (kbytes)
32 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
25
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ATmega3250-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250P-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250P-20AU
Manufacturer:
AT
Quantity:
20 000
Part Number:
ATmega3250V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.9
9.9.1
9.10
9.10.1
2570N–AVR–05/11
System Clock Prescaler
Register Description
Switching Time
OSCCAL – Oscillator Calibration Register
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See
description on selecting external clock as input instead of a 32kHz crystal.
The Atmel ATmega325/3250/645/6450 system clock can be divided by setting the
Clock Prescale Register” on page
when the requirement for processing power is low. This can be used with all clock source
options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
2 on page
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
Bit
(0x66)
Read/Write
Initial Value
ADC
, clk
CPU
300. Calibration outside that range is not guaranteed.
Table 28-2 on page
, and clk
CAL7
R/W
7
FLASH
CAL6
R/W
6
“Asynchronous Operation of Timer/Counter2” on page 141
are divided by a factor as shown in
CAL5
R/W
5
300. The application software can write this register to change
Device Specific Calibration Value
33. This feature can be used to decrease power consumption
CAL4
R/W
4
ATmega325/3250/645/6450
CAL3
R/W
3
CAL2
R/W
2
Table 9-11 on page
CAL1
R/W
1
CAL0
R/W
0
OSCCAL
33.
“CLKPR –
for further
Table 28-
I/O
32
,