AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 20

• Manufacturer Part Number: AT32UC3A3256S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256S

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3. Pipeline
3.1
3.2
3.3
32002F–03/2010
Overview
Prefetch unit
Decode unit
AVR32UC is a pipelined processor with three pipeline stages: IF, ID and EX. All instructions are
issued and complete in order. Some instructions may require several iterations through the EX
stage in order to complete.
The following figure shows an overview of the AVR32UC pipeline stages.
Figure 3-1.
The follwing abbreviations are used in the figure:
The prefetch unit comprises the IF pipestage, and is responsible for feeding instructions to the
decode unit. The prefetch unit fetches 32 bits at a time from the instruction memory interface
and places them in a FIFO prefetch buffer. At the same time, one instruction, either RISC
extended or compact, is fed to the decode stage.
The decode unit generates the necessary signals in order for the instruction to execute correctly.
The ID stage accepts one instruction each clock cycle from the prefetch unit. This instruction is
then decoded, and control signals and register file addresses are generated. If the instruction
cannot be decoded, an illegal instruction or unimplemented instruction exception is issued. The
ID stage also contains a state machine required for controlling multicycle instructions.
The ID stage performs the remapping of register file addresses from logical to physical
addresses. This is used for remapping the stack pointer register into the SP_APP or SP_SYS
registers.
• IF - Instruction Fetch
• ID - Instruction Decode
• EX - Instruction Execute
• MUL - Multiplier
• ALU - Arithmetic-Logic Unit
• LS - Load/Store Unit
P re fe tc h u n it
IF
The AVR32UC pipeline stages.
D e c o d e u n it
ID
R e g file
R e a d
M U L
A L U
L S
R e g file
w rite
M u ltip ly u n it
L o a d -s to re
AVR32
A L U u n it
u n it
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