AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 104

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.14.7
32002F–03/2010
Development Control Register (DC)
DC is used for basic development control of the CPU.
Table 9-11.
R/W
R/W
S
R/W
R/W
R/W
R
R/W
R/W
Bit Number
31
30
29
28
27
26
25
24
Development Control Register
Field Name
ABORT
RES
MM
ORP
RID
Reserved
TOZ
IFM
Init. Val.
0
0
0
0
0
0
0
0
Description
ABORT
Writing ABORT to one while DBE is asserted
causes the CPU to enter Debug Mode, regardless
of SR:DM and any pending exceptions. If the CPU
was in sleep mode, it will first be woken up before
entering Debug Mode. The ABORT bit is cleared
automatically when Debug Mode is entered.
RES - Application Reset
Writing this bit causes an application reset, which
will reset the CPU and other system modules. The
OCD state machines will be reset and the Transmit
Queue flushed, but the OCD control and
configuration registers will not be cleared.
MM - Monitor Mode
1 = The CPU will enter Debug Mode in Monitor
Mode
0 = The CPU will enter Debug Mode in OCD Mode
Changing this bit in Debug Mode does not take
effect until the CPU enters Debug Mode the next
time.
ORP - OCD Register Protect
0 = OCD registers can be written by any privileged
CPU mode
1= OCD registers can be written only in Debug
Mode
RID - Run In Debug
0: Peripherals are frozen in Debug Mode
1: Peripherals keep running in Debug Mode.
In addition the PDBG register must be configured
with individual masks for each module.
TOZ - Trap Opcode Zero
0: The opcode 0x0000 is executed as a normal
CPU instruction
1: The opcode 0x0000 causes entry to Debug
Mode
IFM - Ignore First Match
When written to one, a PC breakpoint on the first
instruction after exiting Debug Mode with the retd
instruction will not trigger re-entry to Debug Mode.
Typically used when returning from a program
breakpoint. This bit stays one until written to zero.
AVR32
104