PEB2047NV2.1 Infineon Technologies AG, PEB2047NV2.1 Datasheet
PEB2047NV2.1
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PEB2047NV2.1 Summary of contents
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ICs for Communications Memory Time Switch Large MTSL PEB 2047 PEB 2047-16 Version 2.1 Data Sheet 03.95 ...
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Edition 03.95 This edition was realized using the software ‚ system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other ...
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PEB 2047 PEB 2047-16 Revision History: Previous Version: Page Page (in Version (in new 01.94) Version) 124 5 127 8 135 16 142 23 143 25 148 31 153 36 154 37 157 40 158 41 159 42 Data Classification ...
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Table of Contents 1 Features ...
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Memory Time Switch Large (MTSL) Preliminary Data 1 Features Non-blocking time/space switch for 2048-, 4096-, 8192 384-kbit/s PCM systems Different modes programmable for input and output separately Configurable for a 4096-kHz, 8192-kHz or 16 384-kHz device clock Switching ...
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Pin Configuration (top view) IN3 IN7 IN6 IN2 IN1 IN5 IN4 IN0 IN 8/FS0 IN 9/FS1 IN 10/FS2 Semiconductor Group PEB 2047 13 MTSL 14 ...
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Pin Definitions and Functions Pin No. Symbol Input (I) Output ( IN0 I 11 IN1 I 10 IN2 I 7 IN3 I 13 IN4 I 12 IN5 I 9 IN6 I ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 26 AD0 I/O 27 AD1 I/O 29 AD2 I/O 30 AD3 I/O I/O 31 AD4 32 AD5 I/O 33 AD6 I/O 34 AD7 I/O 38 OUT0 O 37 ...
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Logic Symbol Interface Figure 1 Functional Symbol 1.3 General Device Overview The Siemens Memory Time Switch Large MTSL (PEB 2047 expansion of the MTSC (PEB 2045) regarding capacity and/or functionality ...
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System Integration The main application field for the MTSL (PEB 2047) are central switches with high switching capacity. Two possibilities exist to implement a non-blocking switch for 1024 input and 1024 output channels. With a 16 384-kHz device clock ...
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Due to the tristate capability of the MTSL larger switches can be easily formed. Figure 4 and 5 show how 4 devices operating with a 16 384-kHz clock or 8 devices operating with a 8192-kHz clock can be arranged to ...
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Functional Description The MTSL is a memory time switch device. Operating with a device clock of 8192 kHz it can connect any of 1024 PCM-input channels to any of 512 output channels. With a device clock of 16 384 ...
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Constant delay (D12 = 0): Minimal delay (D12 = 1): The synchronization of this procedure will be achieved by a rising edge of the synchron pulse SP, which is always sampled with the falling edge of the device clock. Different ...
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AD0... AD7 A0...A1 ALE P Interface INT Figure 7 Block Diagram MTSL The standard 8-bit P interface can communicate with Intel multiplexed/demultiplexed microprocessors as well as with Motorola demultiplexed processors. It gives access to the internal registers ...
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MTSL Internal Timing and Channel Delay Figure 7 shows the chip internal timing of writing and reading the data memory for all possible operation modes. Control Memory Reset Initialization of the device after a hardware reset (RES) is easily ...
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Data Rate/Mbit/s x 1.024 Clock Freq./MHz x 1.024 Input Device Clock Output ...
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For a system operating with 8192-kHz device clock and 8192-Mbit/s/8192 Mbit/s input/output data rate the following frame delay table can be deduced from the timing diagram: Table 1 Input Time-Slot Switched to OUT1 118 – 119 120 – ...
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Operational Description 3.1 Initialization Procedure For a proper initialization of the MTSL the following procedure is recommended: First a reset pulse (RES least two CLK clock-periods has to be applied. All registers contain now their reset values. ...
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Frame Evaluation Suppose the following timing at PCM input IN5 (mode 2): SP CLK 127 Figure 9 If the device is in synchronized state (STAR:PSS = 1) and the command “frame evaluation at FS5” ...
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Input Offset and Output Offset Based on the results of the frame evaluation procedures the input offsets can be adjusted by programming ICSR (7:0) corresponding to inputs IN (7:0). If data oversampling is used, the values of ICSR (7:0) ...
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Detailed Register Description 4.1 Mode Register (MOD) Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value Bit 7 PSB MD2 PSB PCM Stand By; a logical 0 switches the PCM-interface outputs to ...
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IMD2 … IMD0: Input Mode 2, 1 and 0; these bits define the PCM-input mode according to the following table. Table 3 Input Modes Device Clock MD2 Input Mode [kHz] IMD (2:0) 4.096 8.192 ...
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Command Register (CMDR) Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Address Bit 7 0 FSAD2 FSAD1 FSAD (2:0) Frame Synchronization signal Address Address of the chosen FS signal 0 ...
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Status Register (STAR) Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value Bit 7 Z FSAD2 FSAD1 Z Incomplete instruction; a three byte indirect instruction is not completed (Z = 1). FSAD ...
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Interrupt Status Register (ISTA) Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value Bit FEC Frame Evaluation Completed; the indirect register FER contains a valid offset and can be ...
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Indirect Access Register (IAR) Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value: Only the control bits C (1:0) and WR/RDQ are initialized indirect access is performed by reading/writing three consecutive ...
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Table 5 Indirect Access Codes C1 C0 WR/RDQ D12 This bit is only used as a data bit in ...
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Table 6 Input Time-Slot Mapping Input Mode D12 D10 0,4 MD TSC D12 D10 D9 MD TSC 1,5 D12 D10 D9 MD TSC D12 D10 D9 2,6 MD TSC D12 D10 ...
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The control memory address is transformed to the output time-slots: Table 7 Output Time-Slot Mapping Output Mode IA9 IA8 0 IA9 IA8 1 IA9 IA8 IA9 IA8 3 Note: IA9 is only valid within applications with a 16.384-MHz device clock. ...
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Indirect Registers Input Clock Shift Registers ICSR (7:0) Read/write at indirect address IA (3: Reset value Bit 7 ADSR 1 ADSR Add Shift Register; a three bit shift register is inserted into the corresponding input(s). ...
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Input Timing SP CLK TS 0, Bit 7 IN Bit 7 IN# IN# Figure 12 Device Clock = 2 Data Rate SP CLK TS 0, Bit 7 Bit 6 Bit 6 IN Bit 7 IN# TS ...
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SP CLK TS 0, Bit 7 IN Bit 7 IN# IN# Figure 14 Device Clock = 4 Data Rate Operation Control Register (OPCR) Read/write at indirect address IA (3: Reset value Bit 7 1 ...
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Output Clock Shift Register (OSCR) Read/write at indirect address IA (3: Reset value This register determines the clock shift for all outputs. Bit 7 VN2 VN1 OCS (3:0) Output Clock Shift XFE Transmit on Falling Edge ...
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VN (2:0) Version Number according to the table below: Table 9 Version Number VN2 VN1 VN0 Frame Evaluation Register (FER) Read at indirect address IA (3: Reset value = XXX After a ...
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Definition of the calculated offset value: SP CLK Offset Value 0 1 Figure 16 Formulas for Offset Calculation Note: The device must be synchronized to SP (STAR: PSS = 1) in order to generate a correct result in FER. Semiconductor ...
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Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage at any pin with respect to ground Maximum voltage on any pin Note: Stresses above those listed here may cause permanent damage to the device. Exposure ...
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AC Characteristics Ambient temperature under bias range, Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V ...
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AD0 - AD7 Figure 18 P-Read Cycle AD0 -AD7 Figure 19 P-Write Cycle Semiconductor Group Data Data 38 ...
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ALE AD0 - AD7 Figure 20 Multiplexed Address Timing Figure 21 Demultiplexed Address Timing Semiconductor Group ALS ...
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Motorola Bus Mode R Figure 22 P-Read Cycle R AD0 - AD7 Figure 23 P-Write Cycle AD0 - AD5 Figure 24 Address Timing Semiconductor Group t DSD t ...
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PCM-Interface Characteristics Parameter Clock period Clock period low Clock period high Clock period Clock period low Clock period high Frame setup time Frame hold time Serial data input setup time Serial data input hold time Serial data input setup time ...
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CLK OUT (OSCR:XFE = 0) IN (ISCR:RRE = 0) OUT (OSCR:XFE = 1) IN (ICSR:RRE = 1) OUT (OCSR:XFE = 0) IN (OCSR:RRE = 0) OUT (OCSR:XFE = 1) IN (ICSR:RRE = 1) Figure 25 AC Characteristics ...
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CLK (ICSR:RRE = 0) IN (ICSR:RRE=1) Figure 26 AC Characteristics at the PCM Interface Semiconductor Group CPH t CPL PEB 2047 PEB 2047- ...
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Applications 6.1 Determination of MTSL Frame Delay When switching time slots from the input of the MTSL to its output, the question often arises whether the incoming channel is transmitted in the same frame (0 frame delay), the next ...
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Determine the constant M. The value for M can be determined by selecting the corresponding row in the table below ( for your configuration. e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz ...
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By inserting the obtained values for K, M and delays may be calculated for every timeslot (TS). Input … – … – … – ...
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Frame Delay for OUT0 with Input TS Minimal Delay = 0 frame for Output … … … – constant delay ...
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Example for a MTSL Design guaranteeing Constant Frame Delay for all Time Slots In order to achieve a constant frame delay of all PCM channels switched from input to output, the following work-around is suggested. The device is operated ...
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For a 8 MHz/8 MHz-system for example the following frame delay table can be deduced from the timing diagram: Table 10 Frame Delay Input Time-Slot IN0 ... IN4 or 0 – 2 – 4 – (IN4 ... IN7 switched to ...
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Package Outlines Plastic Package, P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 50 PEB 2047 PEB 2047-16 ...