M5M29KB331AVP Renesas Electronics Corporation., M5M29KB331AVP Datasheet
M5M29KB331AVP
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M5M29KB331AVP Summary of contents
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DESCRIPTION The M5M29KB/T331AVP are 3.3V-only high speed 33,554,432-bit CMOS boot block FLASH Memories with alternating BGO(Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously ...
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Flash Memory Block Diagram A0 to A20 CE# OE# WE# WP# RP# BYTE# Capacitance Symbol Parameter Input A20-A0, OE#, WE#, CE#, WP#, CIN capacitance RP#,BYTE# Output COUT DQ15-DQ0,RY/BY# Capacitance 2 M5M29KB/T331AVP 33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS ...
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Flash Memory Part Description The 32M-bit DINOR IV(Divided bit line NOR IV) Flash Memory is 3.3V-only high speed 33,554,432-bit CMOS boot block Flash Memory. Alternating BGO(Back Ground Operation) feature of the device allows Program or Erase operations to be performed ...
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Block Diagram (32Mbit Flash Memory) A20 A19 A18 A17 A16 A15 X-Decoder A14 A13 A12 A11 Address A10 Input Y-Decoder Status / ID Register Chip CE# Enable Output Enable OE# ...
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Function of Flash Memory The 32M-bit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface ...
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Software Command Definitions The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep power ...
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Flash to Page Buffer Command (F1H/D0H) Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm command of D0H. An address within the page to be loaded ...
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Block Organization 32M-bit DINOR(IV) Flash Memory Map (Bottom Boot) x8 (Byte x16 (Word Mode) Mode) 1B0000H- D8000H- 32Kw ord MAIN BLOCK 34 1BFFFFH DFFFFH 1A0000H- D0000H- 32Kw ord MAIN BLOCK 33 1AFFFFH D7FFFH 190000H- C8000H- 32Kw ord MAIN BLOCK 32 ...
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Block Organization 32M-bit DINOR(IV) Flash Memory Map (Top Boot) x8 (Byte x16 (Word Mode) Mode) 230000H- 118000H- 32Kw ord MAIN BLOCK 35 23FFFFH 11FFFFH 220000H- 110000H- 32Kw ord MAIN BLOCK 34 22FFFFH 117FFFH 210000H- 108000H- 32Kw ord MAIN BLOCK 33 ...
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Bus Operation BYTE#=VIH Pins CE# Mode Array VIL Page VIL Read Status Register VIL Identifier Code VIL Output Disable VIL Program VIL Write Erase VIL Others VIL Stand by VIH 1) Deep Power Down X BYTE#=VIL Pins CE# Mode Array ...
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Software Command Definition Command List (WP# =VIH or VIL) 1st Bus Cycle Command Address Mode Read Array Write X Page Read Write X 2) Device Identifier Write Bank 2) Read Status Register Write Bank Clear Status Register Write X 2) ...
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Software Command Definition Command List (WP# =VIL) Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are needed for page program operation. Setup Command for Software Lock Release Mode Word/Byte Program Write Page Program Write Page ...
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Block Locking RP# WP# Bank(I) Boot Parameter/Main VIL X Locked VIL Locked VIH VIH Unlocked WP# pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0). Status Register Symbol Status (I/O Pin) S.R. 7 (DQ7) ...
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Device ID Code Pins A0 Code Manufacturer Code VIL Device Code (Top Boot) VIH Device Code (Bottom Boot) VIH In the case of word mode,The output of upper byte data (DQ15-DQ8) is “0H”. Absolute Maximum Ratings Symbol Parameter VCC VCC ...
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AC electrical characteristics Read Only Mode Symbol tRC tAVAV Read Cycle Time ta(AD) tAVQV Address Access Time ta(CE) tELQV Chip Enable Access Time ta(OE) tGLQV Output Enable Access Time ta(PAD) Page Read Access Time (after 2nd access) tCEPH CE# "H"Pulse ...
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AC electrical characteristics Read / Write Mode (WE# control) Symbol tWC tAVAV Write Cycle Time tAS tAVWH Address Setup Time tAH tWHAX Address Hold Time tDS tDVWH Data Setup Time tDH tWHDX Data Hold Time tOEH tWHGL OE# Hold from ...
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Program / Erase Time Parameter Block Erase Time Main Block Write Time (Byte Mode) Main Block Write Time (Word Mode) Page Write Time Flash to Page Buffer Time Program Suspend / Erase Suspend Time Parameter Program Susupend Time Erase Susupend ...
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Flash VCC Power up / down Timing Read /Write Inhibit 3. GND t VCS Waveforms for Read Operation and Test Conditions V ...
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AC waveforms for Page Read Operation V Address (WORD (BYTE CE OE# ...
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AC Waveforms for Word / Byte Program Operation (WE# Control) V ADDRESS IH Bank Address (Word Valid (Byte CE OE# ...
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AC Waveforms for Page Program Operation (WE# Control) V ADDRESS IH Address Valid Bank Address Valid A20- (Word (Byte CE ...
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AC Waveforms for Erase Operation (WE# Control) V ADDRESS IH Bank Address Valid (Word (Byte CE OE ...
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AC Waveforms for Word / Byte Program Operation with BGO (WE# Control) V ADDRESS IH Bank Address Valid (Word (Byte ...
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AC Waveforms for Page Program Operation with BGO (WE# Control) V ADDRESS IH Bank Address A -A Valid (Word (Byte ...
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AC Waveforms for Erase Operation with BGO (WE# Control) Program in one bank ADDRESS Bank Address 0 (Word Valid (Byte CE ...
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AC Waveforms for Suspend Operation (WE# Control) ADDRESS V IH Bank Address Valid (Word (Byte CE OE ...
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Word / Byte Program Flow Chart Start Write 40H Write Address, Data Status Register Read NO Write SR B0H? YES YES Full Status Check If Desired Suspend Loop Write D0H Word / Byte Program Completed YES Block Erase ...
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Single Data Load to Page Buffer Flow Chart Start Write 74H Write Address, Data NO Load Finished? YES Single Data Load To Page Buffer Completed Page Buffer to Flash Flow Chart Start Write 0EH Write D0H Page Address Status Register ...
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Operation Status (WP#=VIH) 50H Clear Status Register Back Bank Read State Read Array (Random Read) Change Bank Address 3) Others D0H Setup State 74H 55H Flash to Single Data Load Clear Page Buffer Page Buffer to Page Buffer Setup Setup ...
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Operation Status (WP#=VIL) 50H Clear Status Register Back Bank Read State Read Array (Random Read) Change Bank Address D0H 4) Others WD Read Array Change Bank (Random Read) Address 55H 74H Setup State Flash to Single Data Load Clear Page ...
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Package Dimension 31 M5M29KB/T331AVP 33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Renesas LSIs 48P3R-C Rev.1.0_48a_bezz ...
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Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with ...