KM48C8000CS-6 Samsung, KM48C8000CS-6 Datasheet

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KM48C8000CS-6

Manufacturer Part Number
KM48C8000CS-6
Description
8M x 8-Bit CMOS Dynamic RAM with Fast Page Mode
Manufacturer
Samsung
Datasheet
KM48C8000C, KM48C8100C
• Performance Range
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6), package type (SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 8Mx8 Fast Page
Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and
high reliability.
FEATURES
• Part Identification
• Refresh Cycles
* Access mode & RAS only refresh mode
• Active Power Dissipation
KM48C8000C*
KM48C8100C
Speed
CAS-before-RAS & Hidden refresh mode
- KM48C8000C(5.0V, 8K Ref.)
- KM48C8100C(5.0V, 4K Ref.)
: 8K cycle/64ms
: 4K cycle/64ms
-5
-6
Speed
-5
-6
Part
NO.
50ns
60ns
t
RAC
Refresh
cycle
13ns
15ns
8K
4K
t
495
440
CAC
8K
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
110ns
90ns
t
Refresh time
RC
Normal
64ms
660
605
4K
Unit : mW
35ns
40ns
t
PC
DESCRIPTION
(A0~A11)*1
(A0~A10)*1
A0~A12
A0~A9
RAS
CAS
W
FUNCTIONAL BLOCK DIAGRAM
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V 10% power supply
Note) *1 : 4K Refresh
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Memory Array
8,388,608 x 8
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ7
to

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KM48C8000CS-6 Summary of contents

Page 1

... Refresh cycle(4K Ref Ref.), access time ( -5 or -6), package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. ...

Page 2

KM48C8000C, KM48C8100C • KM48C80(1)00CK DQ0 2 DQ1 3 DQ2 4 DQ3 5 N RAS ...

Page 3

KM48C8000C, KM48C8100C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM48C8000C, KM48C8100C DC AND OPERATING CHARACTERISTICS Symbol Power I Don t care CC1 I Normal Don t care CC2 I Don t care CC3 I Don t care CC4 I Normal Don t care CC5 I Don t care CC6 ...

Page 5

KM48C8000C, KM48C8100C CAPACITANCE (T = Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ7] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.4V CC Parameter ...

Page 6

KM48C8000C, KM48C8100C AC CHARACTERISTICS (Continued) Parameter Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS ...

Page 7

KM48C8000C, KM48C8100C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM48C8000C, KM48C8100C NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved (min) and V (max) are reference levels for measuring ...

Page 9

KM48C8000C, KM48C8100C READ CYCLE RAS CAS ASR ADDRESS ...

Page 10

KM48C8000C, KM48C8100C WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CAS ASR ADDRESS ...

Page 11

KM48C8000C, KM48C8100C WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CAS ASR ADDRESS ...

Page 12

KM48C8000C, KM48C8100C READ - MODIFY - WRTIE CYCLE RAS CRP CAS ASR ROW A ADDR ...

Page 13

KM48C8000C, KM48C8100C FAST PAGE READ CYCLE RAS CRP CAS ASR ROW A ADDR ...

Page 14

KM48C8000C, KM48C8100C FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ROW A ADDR ...

Page 15

KM48C8000C, KM48C8100C FAST PAGE READ - MODIFY - WRITE CYCLE RAS RCD CAS RAD t ASR ROW A ADDR ...

Page 16

KM48C8000C, KM48C8100C RAS - ONLY REFRESH CYCLE NOTE : W, OE Don t care OPEN OUT RAS CRP CAS ASR V ...

Page 17

KM48C8000C, KM48C8100C HIDDEN REFRESH CYCLE ( READ ) RAS CRP CAS ASR ADDRESS ...

Page 18

KM48C8000C, KM48C8100C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CAS ASR ADDRESS ...

Page 19

KM48C8000C, KM48C8100C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS CAS DQ0 ~ DQ3( ...

Page 20

KM48C8000C, KM48C8100C PACKAGE DIMENSION 32 SOJ 400mil #32 #1 0.0375 (0.95) 0.050 (1.27) 32 TSOP(II) 400mil 0.037 (0.95) 0.050 (1.27) 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.841 (21.35) MAX 0.821 (20.85) ...

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