K7B161825A-QC75 Samsung, K7B161825A-QC75 Datasheet
K7B161825A-QC75
Related parts for K7B161825A-QC75
K7B161825A-QC75 Summary of contents
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... K7B163625A K7B161825A Document Title 512Kx36 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. History 0.0 1. Initial draft 0.1 1. Add JTAG Scan Order 0.2 1. Add x32 org and industrial temperature . 2. Add 165FBGA package 1.0 1. Final spec release 1.1 1. Delete 119BGA package. 2. Correct the Ball Size of 165 FBGA. ...
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... K7B163625A K7B161825A 16Mb SB/SPB Synchronous SRAM Ordering Information Org. Part Number K7B161825A-QC(I)75/85 1Mx18 K7A161800A-QC(I)25/16/14 K7A161801A-QC(I)20/16 K7B163625A-QC(I)75/85 512Kx36 K7A163600A-QC(I)25/16/14 K7A163601A-QC(I)20/16 512Kx36 & 1Mx18 Synchronous SRAM Speed Mode VDD SB ; Access Time(ns) SPB ; Cycle Time(MHz) SB 3.3 7.5/8.5ns SPB(2E1D) 3.3 250/167/138MHz SPB(2E2D) 3.3 200/167MHz SB 3.3 7.5/8.5ns SPB(2E1D) 3.3 250/167/138MHz SPB(2E2D) 3 ...
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... LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The K7B163625A and K7B161825A are fabricated using SAM- -75 -85 Unit SUNG s high performance CMOS technology and is available in a 100pin TQFP package ...
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... K7B163625A K7B161825A PIN CONFIGURATION (TOP VIEW) NC/DQPc 1 DQc 0 2 DQc DDQ 4 V SSQ 5 DQc 2 6 DQc 3 7 DQc 4 8 DQc SSQ 10 V DDQ 11 DQc 6 12 DQc DQd 0 18 DQd DDQ 20 V SSQ 21 DQd ...
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... Burst Mode Control Notes : 1. A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired 512Kx36 & 1Mx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7B161825A(1Mx18) TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42 V Power Supply(+3.3V) DD 43,44,45,46,47,48,49 V Ground ...
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... K7B161825A FUNCTION DESCRIPTION The K7B163625A and K7B161825A are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. ...
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... K7B163625A K7B161825A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADSP ADSC ...
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... K7B163625A K7B161825A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Voltage on I/O Pin Relative Power Dissipation Storage Temperature ...
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... K7B163625A K7B161825A DC ELECTRICAL CHARACTERISTICS Parameter Symbol Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) Notes : 1. The above parameters are also guaranteed at industrial temperature range. ...
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... K7B163625A K7B161825A Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 11 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 12 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 13 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 14 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 15 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 16 - Nov. 2003 Rev 2.0 ...
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... K7B163625A K7B161825A APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address A [0:19] CLK Microprocessor ADS INTERLEAVE READ TIMING ...
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... K7B163625A K7B161825A APPLICATION INFORMATION DEPTH EXPANSION The Samsung 1Mx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic. Data Address A [0:20] CLK Microprocessor ADS INTERLEAVE READ TIMING ...
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... K7B163625A K7B161825A PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 512Kx36 & 1Mx18 Synchronous SRAM 22.00 0.30 20.00 0.20 (0.58) 0.30 0.10 0.10 MAX 1.40 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 16.00 0.30 0.10 MAX 14.00 0.20 (0.83) 0.50 0.10 0.10 1.60 MAX Nov. 2003 Rev 2.0 ...