DSP56L307VF160 Motorola, DSP56L307VF160 Datasheet

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... XTAL RESET convolution-based PINIT/NMI algorithms. The Motorola DSP56L307, a member of the DSP56300 Digital Signal Processor (DSP) family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations, enhancing signal quality with no impact on channel throughput or total channels supported ...

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Table of Contents DSP56L307 Features ......................................................................................................................................... iii Target Applications ..............................................................................................................................................v Product Documentation........................................................................................................................................v Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings.............................................................................................................................................. 1-1 1.2 Power................................................................................................................................................................ 1-3 1.3 Ground.............................................................................................................................................................. 1-3 1.4 Clock ................................................................................................................................................................ 1-4 1.5 PLL................................................................................................................................................................... 1-4 1.6 External Memory Expansion Port (Port ...

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DSP56L307 Features High-Performance DSP56300 Core • 160 million instructions per second (MIPS) (290 MIPS using the EFCOP in filtering applications) with a 160 MHz clock at 1.8 V core and 3.3 V I/O • Object code compatible with the DSP56000 ...

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On-Chip Memories • 192 24-bit bootstrap ROM • RAM total • Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: Program Instruction RAM Size Cache Size 16 K 24-bit 24-bit ...

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... DSP56L307 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for details.) • A local Motorola distributor • A Motorola semiconductor sales office • A Motorola Literature Distribution Center • The World Wide Web (WWW) Name DSP56300 Family Manual DSP56L307 User’ ...

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vi ...

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Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The DSP56L307 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56L307 signals by functional group. The remainder of this chapter describes the ...

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Signal Groupings V CCP V CCQL V CCQH V CCA V CCD V CCC V CCH V CCS GND P GND P1 GND EXTAL XTAL 4 CLKOUT PCAP After During Reset Reset PINIT NMI A[0–17] D[0–23] AA0/RAS0– 4 AA3/RAS3 RD ...

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Power Power Name V CCP V CCQL V CCQH V CCA V CCD V CCC V CCH V CCS Note: The user must provide adequate external decoupling capacitors for all power connections. 1.3 Ground Ground Name GND P GND ...

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Clock 1.4 Clock Signal Name EXTAL XTAL 1.5 PLL Signal Name CLKOUT PCAP PINIT NMI 1-4 Table 1-4. Clock Signals State Type During Reset Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an ...

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External Memory Expansion Port (Port A) Note: When the DSP56L307 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: RD 1.6.1 External Address Bus Signal Name A[0–17] 1.6.2 External ...

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External Memory Expansion Port (Port A) 1.6.3 External Bus Control Signal Name AA[0–3] RAS[0– 1-6 Table 1-8. External Bus Control Signals State During Type Reset, Stop, or Wait Output Tri-stated Address Attribute—When defined as AA, these signals ...

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Table 1-8. External Bus Control Signals (Continued) State During Signal Type Reset, Stop, or Name Wait BR Output Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains ...

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Interrupt and Mode Control 1.7 Interrupt and Mode Control The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET Signal Name MODA IRQA MODB IRQB MODC IRQC MODD IRQD RESET ...

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Host Interface (HI08) The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs, and ...

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Host Interface (HI08) Signal Name HA0 HAS/HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS/HCS HA10 PB13 1-10 Table 1-11. Host Interface (Continued) State During Type 1,2 Reset Input Ignored Input Host Address Input 0—When the HI08 is programmed to ...

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Table 1-11. Host Interface (Continued) State During Signal Name Type Reset HRW Input Ignored Input HRD/HRD Input PB11 Input or Output HDS/HDS Input Ignored Input HWR/HWR Input PB12 Input or Output HREQ/HREQ Output Ignored Input HTRQ/HTRQ Output PB14 Input or ...

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Host Interface (HI08) Signal Name HACK/HACK HRRQ/HRRQ PB15 Notes: 1-12 Table 1-11. Host Interface (Continued) State During Type 1,2 Reset Input Ignored Input Host Acknowledge—When the HI08 is programmed to interface with a single host request host bus and the ...

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... Enhanced Synchronous Serial Interface 0 (ESSI0) Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola serial peripheral interface (SPI). Signal Name SC00 ...

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Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SRD0 PC4 STD0 PC5 Notes: 1.10 Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SC10 PD0 SC11 PD1 1-14 Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued) State During Type 1,2 Reset ...

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Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued) State During Signal Name Type Reset SC12 Input/Output Ignored Input PD2 Input or Output SCK1 Input/Output Ignored Input PD3 Input or Output SRD1 Input Ignored Input PD4 Input or Output STD1 Output ...

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Serial Communication Interface (SCI) 1.11 Serial Communication Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Signal Name RXD PE0 TXD PE1 SCLK PE2 Notes: 1-16 Table 1-14. ...

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Timers The DSP56L307 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56L307 after a specified number of events (clocks) or signal an external device after counting a specific ...

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JTAG and OnCE Interface 1.13 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56L307 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the ...

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Chapter 2 Specifications 2.1 Introduction The DSP56L307 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. Note: The DSP56L307 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized ...

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Thermal Characteristics Supply Voltage Input/Output Supply Voltage All input voltages Current drain per pin excluding V Operating temperature range Storage temperature Notes: 2.3 Thermal Characteristics Junction-to-ambient, natural convection, single-layer board (1s) Junction-to-ambient, natural convection, four-layer board (2s2p) Junction-to-ambient, @200 ft/min ...

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DC Electrical Characteristics Supply voltage: • Core (V • I/O (V CCQH Input high voltage • D[0–23], BG, BB, TA • MOD/IRQ JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL Input low voltage • D[0–23], BG, BB, TA, MOD/IRQ • All JTAG/ESSI/SCI/Timer/HI08 pins ...

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AC Electrical Characteristics 2.5 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with 0.3 V and a V shown in Note 6 of the previous table. AC timing specifications, which ...

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External Clock Operation The DSP56L307 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1 ...

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AC Electrical Characteristics No. Characteristics 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should maximum EXTAL input high • With PLL disabled (46.7%–53.3% duty cycle • ...

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Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 8 Delay from RESET assertion to all pins at reset value 4 9 Required RESET duration • Power on, external clock ...

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AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 26 Duration of level sensitive IRQA assertion to ensure interrupt 2, 3 service (when exiting Stop) • PLL is not active during Stop (PCTL Bit 17 ...

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RESET 8 All Pins A[0–17] Figure 2-3. Reset Timing A[0–17 IRQA, IRQB, IRQC, IRQD, NMI a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General-Purpose I/O Figure 2-4. External Fast Interrupt ...

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AC Electrical Characteristics IRQC, IRQD, NMI IRQC, IRQD, NMI MODA, MODB, MODC, MODD, PINIT 2-10 IRQA, IRQB, IRQA, IRQB, Figure 2-5. External Interrupt Timing (Negative Edge-Triggered) RESET V V Figure 2-6. Operating Mode Select Timing 24 IRQA A[0–17] Figure 2-7. ...

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IRQA, IRQB, IRQC, IRQD, 2.5.5 External Memory Expansion Port (Port A) 2.5.5.1 SRAM Timing No. 100 Address valid and AA assertion pulse width 101 Address and AA valid to WR assertion 102 WR assertion pulse width 103 WR deassertion to ...

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AC Electrical Characteristics No. 106 RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion 108 Data valid to WR deassertion (data setup time) 109 Data hold time from WR deassertion 110 WR assertion to ...

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Table 2-8. 100 MHz SRAM Timing (Continued) No. Characteristics 117 RD deassertion to address not valid 118 TA setup before deassertion 119 TA hold after deassertion Notes number of BCR-specified wait ...

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AC Electrical Characteristics No. 108 Data valid to WR deassertion (data setup time) 109 Data hold time from WR deassertion 110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active ...

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A[0–17] AA[0–3] 113 D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-10. SRAM Read Access A[0–17] AA[0–3] 101 ...

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AC Electrical Characteristics 2.5.5.2 DRAM Timing The selection guides in Figure 2-12 and Figure 2-15 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four ...

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Table 2-10. DRAM Page Mode Timings, Three Wait States No. Characteristics 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid ...

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AC Electrical Characteristics No. 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data ...

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RAS CAS 137 Column Row A[0–17] Address Add WR RD 155 D[0–23] Data Out Figure 2-13. DRAM Page Mode Write Accesses RAS CAS 137 Row Column A[0–17] Add Address WR RD D[0–23] Figure 2-14. DRAM Page Mode Read Accesses AC ...

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AC Electrical Characteristics Table 2-12. DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to ...

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Table 2-12. DRAM Out-of-Page and Refresh Timings, Eleven Wait States No. Characteristics 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address ...

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AC Electrical Characteristics Table 2-13. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States No. 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS ...

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RAS 169 170 CAS 171 Row Address A[0–17] 177 WR RD D[0–23] Figure 2-16. DRAM Out-of-Page Read Access 157 163 165 167 164 168 166 173 174 175 Column Address 172 176 191 178 160 159 158 192 Data ...

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AC Electrical Characteristics RAS CAS WR 2-24 162 RAS 169 170 CAS 171 Row Address A[0–17 D[0–23] Figure 2-17. DRAM Out-of-Page Write Access 162 190 170 177 Figure 2-18. DRAM Refresh Access 157 163 165 167 164 168 ...

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Synchronous Timings Table 2-14. External Bus Synchronous Timings No. Characteristics 198 CLKOUT high to address, and AA valid 199 CLKOUT high to address, and AA invalid 200 TA valid to CLKOUT high (set-up time) 201 CLKOUT high to TA ...

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AC Electrical Characteristics CLKOUT A[0–17] AA[0–3] D[0–23] D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. 2-26 198 TA WR 210 203 202 ...

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CLKOUT 198 A[0–17] AA[0– 210 203 D[0–23] 202 208 RD D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-20. ...

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AC Electrical Characteristics 2.5.5.4 Arbitration Timings Using CLKOUT ( 100 MHz only) No. 212 CLKOUT high to BR assertion/deassertion 213 BG asserted/deasserted to CLKOUT high (set-up) 214 CLKOUT high to BG deasserted/asserted (hold) 215 BB deassertion to CLKOUT high (input ...

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BG1 BB BG2 Figure 2-21. Asynchronous Bus Arbitration Timing The asynchronous bus arbitration is enabled by internal synchronization circuits on These synchronization circuits add delay from the external signal until it is exposed to internal logic result of ...

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AC Electrical Characteristics 2.5.6 Host Interface Timing No. Characteristic 317 Read data strobe assertion width HACK assertion width 318 Read data strobe deassertion width HACK deassertion width 319 Read data strobe deassertion width 8,11 reads , or between two consecutive ...

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Table 2-17. Host Interface Timings No. Characteristic 337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time 4 after data strobe deassertion 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read 339 Delay from write ...

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AC Electrical Characteristics Figure 2-24. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-32 HA[2–0] HCS 336 HRW HDS H[7–0] HREQ (single host request) HRRQ (double host request) Figure 2-23. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] HCS ...

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HA[2–0] HCS 336 HRW HDS H[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-25. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe Figure 2-26. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 336 337 333 331 337 320 ...

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AC Electrical Characteristics 2-34 , HA[10–8] 322 HAS 336 HRW HDS 334 HAD[7–0] Address HREQ (single host request) HRRQ (double host request) Figure 2-27. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 322 HAS HRD 334 HAD[7–0] Address HREQ ...

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HA[10–8] 322 HAS 336 HRW HDS 334 335 HAD[7–0] Address HREQ (single host request) HTRQ (double host request) Figure 2-29. Write Timing Diagram, Multiplexed Bus, Single Data Strobe , HA[10–8] 322 HAS HWR 334 335 HAD[7–0] Address HREQ (single host ...

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AC Electrical Characteristics 2.5.7 SCI Timing No. Characteristics 400 Synchronous clock cycle 401 Clock low period 402 Clock high period 403 Output data setup to clock falling edge (internal clock) 404 Output data hold after clock rising edge (internal clock) ...

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SCLK (Output) 403 Data Valid TXD Data RXD Valid SCLK (Input) 407 TXD 409 RXD b) External Clock Figure 2-31. SCI Synchronous Mode Timing 1X SCLK (Output) TXD Figure 2-32. SCI Asynchronous Mode Timing 400 402 401 404 405 406 ...

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AC Electrical Characteristics ESSI0/ESSI1 Timing No. 430 Clock cycle 431 Clock high period For internal clock For external clock 432 Clock low period For internal clock For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC ...

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Table 2-19. ESSI Timings at 100 MHz (Continued No. Characteristics 450 TXC rising edge to FST out (wl) high 451 TXC rising edge to FST out (wl) low 452 TXC rising edge to data out enable from ...

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AC Electrical Characteristics No. 430 Clock cycle 431 Clock high period For internal clock For external clock 432 Clock low period For internal clock For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC rising edge ...

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Table 2-8. ESSI Timings at 160 MHz (Continued) 1,2,3 No. Characteristics 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to Transmitter #0 drive enable assertion 454 TXC rising edge to data out valid ...

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AC Electrical Characteristics Note: 2-42 430 431 TXC (Input/ Output) 446 447 FST (Bit) Out 450 FST (Word) Out 454 452 Data Out 459 Transmitter #0 Drive Enable 457 FST (Bit) In 458 FST (Word) In Flags Out In Network ...

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RXC 432 (Input/ Output) 433 434 FSR (Bit) Out 437 FSR (Word) Out Data In 441 FSR (Bit) In FSR (Word) In Flags In Figure 2-2. ESSI Receiver Timing 440 439 Last Bit First Bit 443 443 442 ...

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AC Electrical Characteristics 2.5.9 Timer Timing No. Characteristics 480 TIO Low 481 TIO High 482 Timer set-up time from TIO (Input) assertion to CLKOUT rising edge 483 Synchronous timer delay time from CLKOUT rising edge to the external memory access ...

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TIO (Input) Address 2.5.10 CONSIDERATIONS FOR GPIO USE 2.5.10.1 Operating Frequency of 100 MHz or Less No. 490 CLKOUT edge to GPIO out valid (GPIO out delay time) 491 CLKOUT edge to GPIO out not valid (GPIO out hold time) ...

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AC Electrical Characteristics 2.5.10.2 With an Operating Frequency above 100 MHz The following considerations can be helpful when GPIO is used for output or input with an operating frequency above 100 MHz (that is, when • GPIO as Output: — ...

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JTAG Timing No. 500 501 502 503 504 505 506 507 508 509 510 511 512 513 Notes: TCK (Input) Table 2-3. JTAG Timing Characteristics TCK frequency of operation TCK cycle time in Crystal mode TCK clock pulse width ...

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AC Electrical Characteristics TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) TCK (Input) TRST (Input) 2- 506 507 506 Figure 2-9. Boundary Scan (JTAG) Timing ...

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OnCE Module TimIng No. 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56L307 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time Note: DE Table ...

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AC Electrical Characteristics 2-50 ...

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Chapter 3 Packaging 3.1 Pin-Out and Package Information This section includes diagrams of the DSP56L307 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) package. ...

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MAP-BGA Package Description 3.2 MAP-BGA Package Description Top and bottom views of the MAP-BGA package are shown in Figure 3-1 and Figure 3-2 with their pin-outs SC11 B SRD1 SC12 SC02 STD1 C PINIT SC01 D ...

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D11 D14 D10 D13 D12 CCD GND GND CCD D0 A16 A17 GND GND A15 A14 V GND GND CCQH A12 V ...

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MAP-BGA Package Description Ball No. A1 Not Connected (NC), reserved A2 SC11 or PD1 A3 TMS A4 TDO A5 MODB/IRQB A6 D23 D19 A9 D16 A10 D14 A11 D11 A12 D9 A13 D7 A14 NC B1 SRD1 ...

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Table 3-1. Signal List by Ball Number Ball Ball Signal Name No. No. F6 GND H3 F7 GND H4 F8 GND H5 F9 GND H6 F10 GND H7 F11 GND H8 F12 V H9 CCQH F13 A14 H10 F14 A15 ...

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MAP-BGA Package Description Ball No. L11 GND L12 V L13 A3 L14 A4 M1 HA1, HA8, or PB9 M2 HA2, HA9, or PB10 M3 HA0, HAS/HAS, or PB8 H0, HAD0, or PB0 ...

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Table 3-2. Signal List by Signal Name Ball Signal Name Signal Name No. A0 N14 A1 M13 A10 H13 A11 H14 A12 G14 A13 G12 A14 F13 A15 F14 A16 E13 A17 E12 A2 M14 A3 L13 A4 L14 A5 ...

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MAP-BGA Package Description Signal Name 3-8 Table 3-2. Signal List by Signal Name Ball Signal Name No. GND F11 GND GND G4 GND GND G5 GND GND G6 GND GND G7 GND GND G8 GND GND G9 GND GND G10 ...

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Table 3-2. Signal List by Signal Name Ball Signal Name Signal Name No. IRQA C4 IRQB A5 IRQC C5 IRQD B5 MODA C4 MODB A5 MODC C5 MODD A14 NC B14 P14 NMI ...

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MAP-BGA Package Mechanical Drawing 3.3 MAP-BGA Package Mechanical Drawing Figure 3-3. DSP56L307 Mechanical Information, 196-pin MAP-BGA Package 3-10 ...

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Chapter 4 Design Considerations 4.1 Thermal Design Considerations Equation 1: Equation 2: An estimate of the chip junction temperature, T this equation Where ambient temperature ° ...

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Electrical Design Considerations A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the ...

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Use the following list of recommendations to ensure correct DSP operation. • Provide a low-impedance path from the board power supply to each board ground to each GND pin. • Use at least six 0.01–0.1 F bypass capacitors positioned as ...

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Power Consumption Considerations 4.3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current ...

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PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified ...

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Input (EXTAL) Jitter Requirements 4-6 ...

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Appendix A Power Consumption Benchmark The following benchmark program evaluates DSP56L307 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to ...

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Power Consumption Benchmark clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop XDAT_START ; org ...

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XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc ...

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Power Consumption Benchmark ; ; EQUATES for DSP56L307 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** page opt ioequ ;------------------------------------------------------------------------ ; ; ; ;------------------------------------------------------------------------ ; M_HDR EQU $FFFFC9 M_HDDR EQU $FFFFC8 M_PCRC EQU $FFFFBF M_PRRC ...

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EQUATES for Serial Communications Interface (SCI) ; ;------------------------------------------------------------------------ ; Register Addresses M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high) M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95 ; SCI Transmit Data Register ...

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Power Consumption Benchmark ; M_TX10 EQU $FFFFAC M_TX11 EQU $FFFFAB M_TX12 EQU $FFFFAA M_TSR1 EQU $FFFFA9 M_RX1 EQU $FFFFA8 M_SSISR1 EQU $FFFFA7 M_CRB1 EQU $FFFFA6 M_CRA1 EQU $FFFFA5 M_TSMA1 EQU $FFFFA4 M_TSMB1 EQU $FFFFA3 M_RSMA1 EQU $FFFFA2 M_RSMB1 EQU $FFFFA1 ...

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EQUATES for Exception Processing ; ;------------------------------------------------------------------------ ; Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 ; IRQA Mode ...

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Power Consumption Benchmark M_TLR0 EQU M_TCPR0 EQU $FFFF8D M_TCR0 EQU ; M_TCSR1 EQU $FFFF8B M_TLR1 EQU M_TCPR1 EQU $FFFF89 M_TCR1 EQU ; M_TCSR2 EQU $FFFF87 M_TLR2 EQU M_TCPR2 EQU $FFFF85 M_TCR2 EQU M_TPLR EQU M_TPCR EQU ; M_TE EQU 0 ...

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M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination ...

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Power Consumption Benchmark M_FDBA M_FCBA M_FDCH ;------------------------------------------------------------------------ ; ; ; ;------------------------------------------------------------------------ ; M_PCTL EQU $FFFFFD ; M_MF EQU $FFF M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 M_XTLD EQU 16 M_PSTP EQU 17 M_PEN EQU 18 ...

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SR M_CP EQU $c00000; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ...

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Power Consumption Benchmark I_NMI EQU I_VEC+$0A ;------------------------------------------------------------------------ ; Interrupt Request Pins ;------------------------------------------------------------------------ I_IRQA EQU I_VEC+$10 I_IRQB EQU I_VEC+$12 I_IRQC EQU I_VEC+$14 I_IRQD EQU I_VEC+$16 ;------------------------------------------------------------------------ ; DMA Interrupts ;------------------------------------------------------------------------ I_DMA0 EQU I_VEC+$18 I_DMA1 EQU I_VEC+$1A I_DMA2 EQU I_VEC+$1C I_DMA3 EQU ...

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Index A ac electrical characteristics 2-4 address bus 1-1 applications iv B benchmark test algorithm A-1 block diagram i bootstrap ROM iii Boundary Scan (JTAG Port) timing diagram 2-48 bus address 1-2 control 1-1 data 1-2 external address 1-5 external ...

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Index configuration 1-9 usage considerations 1-9 Host Port Control Register (HPCR) 1-10 Host Request Double 1-2 Single 1-2 Host Request (HR) 1-2 I information sources v instruction cache iii internal clocks 2-4 interrupt and mode control 1-1 interrupt control 1-8 ...

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S Serial Communication Interface (SCI) iii , 1-2 1-16 Asynchronous mode timing 2-37 Synchronous mode timing 2-37 signal groupings 1-1 signals 1-1 functional grouping 1-2 Single Data Strobe 1-2 SRAM read access 2-15 support iv write access 2-15 Stop mode ...

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Index Index-4 ...

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...

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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. OnCE and digital dna are trademarks of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2001, 2002 DSP56L307/D Core Frequency Order Number (MHz) 160 DSP56L307VF160 ...