M5M29KT641AVP Renesas Electronics Corporation., M5M29KT641AVP Datasheet
M5M29KT641AVP
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M5M29KT641AVP Summary of contents
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DESCRIPTION The M5M29KB/T641AVP are 3.3V-only high speed 67,108,864-bit CMOS boot block FLASH Memories with alternating BGO(Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously ...
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Flash Memory Block Diagram A0 to A21 CE# OE# WE# WP# RP# BYTE# Capacitance Symbol Parameter Input A21-A0, OE#, WE#, CE#, WP#, CIN capacitance RP#,BYTE# Output COUT DQ15-DQ0,RY/BY# Capacitance 2 M5M29KB/T641AVP 67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT) CMOS ...
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Flash Memory Part Description The 64M-bit DINOR IV(Divided bit line NOR IV) Flash Memory is 3.3V-only high speed 67,108,864-bit CMOS boot block Flash Memory. Alternating BGO(Back Ground Operation) feature of the device allows Program or Erase operations to be performed ...
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Block Diagram (64Mbit Flash Memory) A21 A20 A19 A18 A17 A16 A15 X-Decoder A14 A13 A12 A11 Address A10 Input Y-Decoder Status / ID Register Chip Enable CE# Output Enable ...
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Function of Flash Memory The 64M-bit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface ...
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Software Command Definitions The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep power ...
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Flash to Page Buffer Command (F1H/D0H) Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm command of D0H. An address within the page to be loaded ...
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Block Organization 64M-bit DINOR(IV) Flash Memory Map (Bottom Boot) x8 (Byte x16 (Word x8 (Byte Mode) Mode) 1A0000H- D0000H- 3C0000H- 32Kword 33 1AFFFFH D7FFFH 3CFFFFH 190000H- C8000H- 3B0000H- 32Kword 32 19FFFFH CFFFFH 3BFFFFH 180000H- C0000H- 3A0000H- 32Kword 31 18FFFFH C7FFFH ...
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Block Organization 64M-bit DINOR(IV) Flash Memory Map (Top Boot) x8 (Byte x16 (Word x8 (Byte Mode) Mode) 210000H- 108000H- 430000H- 32Kword 33 21FFFFH 10FFFFH 43FFFFH 200000H- 100000H- 420000H- 32Kword 32 20FFFFH 107FFFH 42FFFFH 1F0000H- F8000H- 410000H- 32Kword 31 1FFFFFH FFFFFH ...
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Bus Operation Pins CE# Mode Array VIL Status Register VIL Read Identifier Code VIL Page VIL Output Disable VIL Program VIL Write Erase VIL Others VIL Stand by VIH Deep Power Down can be VIH or VIL ...
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Software Command Definition Command List (WP# =VIH or VIL) 1st Bus Cycle Command Mode Address Read Array Write X Write X Page Read 2) Device Identifier Write Bank 2) Write Bank Read Status Register Write X Clear Status Register 2) ...
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Software Command Definition Command List (WP# =VIL) Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are needed for page program operation. Setup Command for Software Lock Release Mode Word/Byte Program Write Page Program Write Page ...
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Block Locking RP# WP# Bank(I) Boot Parameter/Main VIL X Locked VIL Locked VIH VIH Unlocked WP# pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0). Status Register Symbol Status (I/O Pin) S.R. 7 (DQ7) ...
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Device ID Code Pins A0 Code Manufacturer Code VIL Device Code (Top Boot) VIH Device Code (Bottom Boot) VIH The output of upper byte data (DQ15-DQ8) is “0H”. Absolute Maximum Ratings Symbol Parameter VCC VCC Voltage VI1 All Input or ...
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AC electrical characteristics Read Only Mode Symbol tRC tAVAV Read Cycle Time ta(AD) tAVQV Address Access Time ta(CE) tELQV Chip Enable Access Time ta(OE) tGLQV Output Enable Access Time ta(PAD) tPAVQV Page Read Access Time tCEPH CE# "H"Pulse width tCLZ ...
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AC electrical characteristics Read / Write Mode (WE# control) Symbol tWC tAVAV Write Cycle Time tAS tAVWH Address Setup Time tAH tWHAX Address Hold Time tDS tDVWH Data Setup Time tDH tWHDX Data Hold Time tOEH tWHGL OE# Hold from ...
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Program / Erase Time Parameter Block Erase Time Main Block Write Time Page Write Time Flash to Page Buffer Time Program Suspend / Erase Suspend Time Parameter Program Susupend Time Erase Susupend Time Flash VCC Power Up / Down Timing ...
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Flash VCC Power up / down Timing Read /Write Inhibit 3. VHEL GND t VCS Waveforms for Read Operation and Test ...
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AC waveforms for Page Read Operation F- ...
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AC Waveforms for Word/Byte Program Operation (WE# Control Bank Address ADDRESS Valid V IL A21 High-Z ...
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AC Waveforms for Page Program Operation (WE# Control) V ADDRESS IH Address Valid Bank Address Valid A21- BYTE#=VIL BYTE#=VIH CE# ...
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AC Waveforms for Erase Operation (WE# Control ADDRESS Bank Address Valid V A21 WPH WE# V ...
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AC Waveforms for Word/Byte Program Operation with BGO (WE# Control) V ADDRESS IH Bank Address Valid A21 - BYTE#=VIL V (A6-A-1) IH BYTE#=VIH V (A6-A0 CE ...
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AC Waveforms for Page Program Operation with BGO (WE# Control) V ADDRESS IH Bank Address Valid A21- BYTE#=VIL V (A6-A-1) IH BYTE#=VIH V (A6-A0 CE OE# V ...
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AC Waveforms for Erase Operation with BGO (WE# Control) Progtam in a bank V IH ADDRESS Bank Address Valid CE OE WPH V ...
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AC Waveforms for Suspend Operation (WE# Control) V ADDRESS IH Bank Address Valid CE OE WE# V ...
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AC Waveforms for Device ID Read Operation with BBR(Back Bank Read) V ADDRESS IH Bank Address Valid CE OE ...
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Word/Byte Program Flow Chart Start Write 40H Write Address, Data Status Register Read NO Write SR BOH? YES YES Full Status Check If Desired Suspend Loop Write D0H Word Program Completed YES Block Erase Flow Chart Start Write ...
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Single Data Load to Page Buffer Flow Chart Start Write 74H Write Address, Data NO Load Finished? YES Single Data Load To Page Buffer Completed Page Buffer to Flash Flow Chart Start Write 0EH Write D0H Page Address Status Register ...
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Operation Status (WP#=VIH) 50H Clear Status Register Back Bank Read State Read Array (Random Read) Change Bank Address 3) Others D0H Setup State 74H 55H Flash to Single Data Load Clear Page Buffer Page Buffer to Page Buffer Setup Setup ...
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Operation Status (WP#=VIL) 50H Clear Status Register Back Bank Read State Read Array (Random Read) Change Bank Address D0H 4) Others WD Read Array Change Bank (Random Read) Address 55H Setup State 74H Flash to Single Data Load Clear Page ...
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Package Dimension 32 M5M29KB/T641AVP 67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Renesas LSIs 48P3R-C Rev.1.3_48a_bezz ...
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Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with ...