GMZAN3L GMI, GMZAN3L Datasheet
GMZAN3L
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GMZAN3L Summary of contents
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PRELIMINARY DATA SHEET XGA Analog Interface LCD Monitor Controller GENESIS MICROCHIP 165 Commerce Valley Dr. West • Thornhill • ON • Canada • L3T 7V8 • Tel: (905) 889-5400 • Fax: (905) 889-5422 2150 Gold Street • PO Box 2150 ...
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The following are trademarks or registered trademarks of Genesis Microchip, Inc Genesis , Genesis Display Perfection TM SureSync , Adaptive Backlight Control™, Faroudja Other brand or product names are trademarks of their respective holders. © Copyright 2003 Genesis ...
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Overview ........................................................................................................................................8 1.1 gmZAN3 System Design Examples ......................................................................................8 1.2 gmZAN3 Features .................................................................................................................9 2 gmZAN3 Pinout ...........................................................................................................................10 3 gmZAN3 Pin List .........................................................................................................................12 4 Functional Description .................................................................................................................19 4.1 Clock Generation.................................................................................................................19 4.1.1 Using the Internal Oscillator with External Crystal ........................................................19 4.1.2 Using ...
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... Programming the Display Timing...................................................................................36 4.8.3 Panel Power Sequencing (PPWR, PBIAS) .....................................................................37 4.8.4 Output Dithering .............................................................................................................38 4.9 Four Channel LVDS Transmitter (for gmZAN3L Only) ....................................................38 4.10 Flexible TTL Outputs (gmZAN3T Only)............................................................................39 4.11 Energy Spectrum Management (ESM)................................................................................39 4.12 OSD .....................................................................................................................................39 4.12.1 On-Chip OSD SRAM .................................................................................................40 4.12.2 Color Look-up Table (LUT) .......................................................................................41 4.13 General Purpose Inputs and Outputs (GPIO’s) ...................................................................41 4 ...
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... Analog Input Port (Common to gmZAN3T and gmZAN3L) .............................................12 Table 1. Clock Pins (Common to gmZAN3T and gmZAN3L).........................................................12 Table 2. System Interface and GPIO Signals (gmZAN3T) ...............................................................13 Table 3. System Interface and GPIO Signals (gmZAN3L) ...............................................................14 Table 4. Display Output Port for (gmZAN3L)..................................................................................15 Table 5. Display Output Port for (gmZAN3T)..................................................................................16 Table 6. ...
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... Figure 1. gmZAN3 System Design Examples..................................................................................8 Figure 2. gmZAN3T Pin Out Diagram...........................................................................................10 Figure 3. gmZAN3L Pin out Diagram............................................................................................11 Figure 4. gmZAN3 Functional Block Diagram ..............................................................................19 Figure 5. Using the Internal Oscillator with External Crystal ........................................................20 Figure 6. Internal Oscillator Output................................................................................................21 Figure 7. Sources of Parasitic Capacitance.....................................................................................22 Figure 8. Using an External Single-ended Clock Oscillator...........................................................22 Figure 9 ...
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... Changed Figure 14 drawing with more clarification • Pin corrections (documentation error): C0523-DAT-01F • gmZAN3L – corrected pins: 40, 43, 52,53, 60, 63 (GPIO[8:13] to GPO[8:13]) • gmZAN3T – corrected pins: 40, 43, 52, 53, 60, 63 • Part Number change: removed hyphen from chip name throughout document • ...
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... TTL output and • gmZAN3L with industry standard single four channel LVDS transmitter for direct connect to LCD panels with LVDS interface. With this level of integration, the gmZAN3 devices simplify and reduce the cost of LCD monitors while maintaining a high-degree of flexibility and quality. ...
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... Swap red and green channels • Ability to reverse bit order of each output • Single or double pixel clock • Support up to XGA 85Hz Built in Flexible LVDS Transmitter for gmZAN3L • Four channel 6/8-bit LVDS transmitter (with high-quality dithering) • Programmable channel swapping and polarity • ...
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These devices are available in a 128-pin Plastic Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals. 1 RESETn RESET_OUT 2 3 VCO_LV 4 AVDD_3.3 5 AVSS 6 PD0/ER0 7 PD1/ER1 8 PD2/ER2 9 PD3/ER3 ...
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... AGND_RED 98 RED- 97 RED+ 96 AVDD_RED_3.3 95 AGND_GREEN 94 GREEN- 93 GREEN+ 92 SOG_MCSS 91 AVDD_GREEN_3.3 90 AGND_BLUE 89 BLUE- 88 BLUE+ 87 AVDD_BLUE_3.3 86 VSYNC 85 HSYNC 84 STI_TM2 83 STI_TM1 82 CRVSS 81 CVDD_1.8 80 GPIO0/PWM0 79 GPIO1/PWM1 78 GPIO2 77 PBIAS 76 CRVSS 75 RVDD_3.3 74 PPWR 73 DCLK 72 DVS 71 DHS 70 DEN 69 RESERVED 68 RESERVED 67 RESERVED 66 RESERVED 65 RESERVED gmZAN3L Pin out Diagram 11 July 2003 ...
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... I/O Legend Analog Input Output Power Ground, I-PU = Input with pull-up, I-PD = Input with pull down, IO-PD = Bidirectional with pull down Table 1. Analog Input Port (Common to gmZAN3T and gmZAN3L) Pin Name No. I/O AVDD_RED_3 RED RED AGND_RED 99 AG AVDD_GREEN_3 SOG_MCSS 92 AI GREEN ...
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System Interface and GPIO Signals (gmZAN3T) Table 3. Pin Name No I/O RESETn 1 IO RESET_OUT 2 O GPIO0/PWM0 80 IO GPIO1/PWM1 79 IO GPIO2 78 IO GPIO3/IRQn 116 IO GPIO4/MEM_REG 117 IO-PD GPIO5/AD7 121 IO GPIO6/AD6 122 IO GPIO7/AD5 ...
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... Table 4. System Interface and GPIO Signals (gmZAN3L) Pin Name No I/O RESETn 1 IO RESET_OUT 2 O GPIO0/PWM0 80 IO GPIO1/PWM1 79 IO GPIO2 78 IO GPIO3/IRQn 116 IO GPIO4/MEM_REG 117 IO-PD GPIO5/AD7 121 IO GPIO6/AD6 122 IO GPIO7/AD5 123 IO GPO8 60 O GPO9 63 O GPO10 52 O GPO11 53 O GPO12 40 O GPO13 43 O HDATA0/ADO/HP0 ...
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... These pin names are based on having swapping enabled on the initial positive and negative LVDS signals. C0523-DAT-01G Display Output Port for (gmZAN3L ...
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Table 6. Pin Name No I/O Description DCLK 73 O Panel output clock. [Tri-state output, Programmable Drive] DVS 72 O Panel Vertical Sync. [Tri-state output, Programmable Drive] DHS 71 O Panel Horizontal Sync. [Tri-state output, Programmable Drive] DEN 70 O ...
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... Reserved Pins for gmZAN3L Reserve Pins for gmZAN3T I/O Power and Ground Pins for gmZAN3L 17 gmZAN3 Preliminary Data Sheet July 2003 ...
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... G 113 G 115 G CVDD_1 Connect to 1.8V digital supply Must be bypassed with a 0.1µF capacitor to CRVSS (as close to the pin as possible 114 P Power and Ground Pins for LVDS Transmitter for gmZAN3L Table 10. Pin Name No I/O AVDD_OUT_LV_3 AVDD_LV_3 AVSS_OUT_LV AVSS_LV 18 G Table 11 ...
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... Output Capture / Shrink / Gamma Data Measure- Filter Control Path ment gmZAN3 Functional Block Diagram 19 gmZAN3 Preliminary Data Sheet Energy Spectrum Manager gmZAN3L LVDS Single Channel Transmitter LVDS Panel Data and Control 24/36/48-bit gmZAN3T TTL Output TTL output to LCD Panel July 2003 ...
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The oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. When the gmZAN3 is in reset, the state of the HDATA2/AD2/OSC_SEL pin is sampled. If the pin is ...
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The output of the comparator is buffered and then distributed to the gmZAN3 circuits. 3.3 Volts ~ 2 Volts Figure 6. One of the design parameters that must ...
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Figure 7. Some attention must be given to the details of the oscillator circuit when used with a crystal resonator. The PCB traces should be as short as possible. The value of C should not be exceeded because of potential ...
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Maximum Duty Cycle 4.1.3 Clock Synthesis The gmZAN3 synthesizes all additional clocks internally as illustrated in Figure 9 below. The synthesized clocks are as follows: 1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK ...
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Hardware Reset Hardware Reset is performed during power-up by the internal power-on reset circuit. The power-on reset (POR) circuit generates two signals: • RESETn: an active-low pulse of around 120ms • RESET_OUT: an active-high pulse with identical timing as ...
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Figure 10. MCU I/O PORT Figure 11. T RESETn +3.3V_AVDD RESETn RESET_OUT Figure 12. C0523-DAT-01G ...
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Note: • The RESETn pin may also be connected to an external momentary contact switch to ground, for a Reset Button feature. • When analog 3.3V reaches the reset threshold (2.5V) an active LOW reset signal is generated (RESETn). The ...
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RED GREEN GREEN DB15 BLUE Hsync Vsync GND HSYNC VSYNC Figure 13. NOTE very important to follow the recommended layout guidelines for the circuit shown in Figure 13. Follow the recommendations in the gmZAN3 Layout Guidelines. For specific ...
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ADC Characteristics The table below summarizes the characteristics of the ADC: Track & Hold Amp Bandwidth Full Scale Adjust Range at RGB Inputs 0.55 V Full Scale Adjust Sensitivity Zero Scale Adjust Sensitivity Sampling Frequency (Fs) 10 MHz Differential ...
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HS SCLK ACLK Phase Delay Input HSync SCLK ACLK Figure 14. 4.3.4 Sampling Phase Adjustment The programmable ADC sampling phase is adjusted by delaying the (input HSYNC aligned) SCLK to produce the ADC clock (ACLK) inside the SDDS. The phase ...
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V iH Input to Schmitt trigger V iL Schmitt trigger output Figure 15. Temperature and Voltage Variation for Schmitt Trigger Table 16. High Threshold Room Temp @ 3.3V 100°C @ 3.0V 0°C @ 3.6V NOTE: The power on default value ...
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XOR - CSYNC NOR – CSYNC: OFF SERRATION: OFF SERRATED (1.0H) SERRATED (0.5 H) Figure 16. 4.3.7 ADC Capture Window Figure 17 below illustrates the capture window used for the ADC input. In the horizontal direction the capture window is ...
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Figure 17. The Reference Point marks the leading edge of the first internal HSYNC following the leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived from external HSYNC and VSYNC inputs. Horizontal parameters ...
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Factory Test Station Figure 19. 4.5 Input Format Measurement The gmZAN3 has an Input Format Measurement block (the IFM) providing the capability of measuring the horizontal and vertical timing parameters of the input video source. This information may be used ...
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Watchdog The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any VSYNC period exceeds the programmed timing threshold (in terms ...
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High-Quality Scaling The gmZAN3 zoom scaler uses an adaptive scaling technique proprietary to Genesis Microchip Inc., and provides high quality scaling of real time video and graphics images. An input field/frame is scalable in both the vertical and horizontal ...
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Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display timing is determined only by ...
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DCLK (Output) DEN (Output) ER/EG/EB (Output) OR/OG/OB (Output) Figure 22. DCLK (Output) DEN (Output) ER/EG/EB (Output) OR/OG/OB (Output) Figure 23. 4.8.3 Panel Power Sequencing (PPWR, PBIAS) gmZAN3 has two dedicated outputs PPWR and PBIAS to control LCD power sequencing once ...
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... All gray scales are available on the panel output whether using 8-bit panel (dithering from bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel). 4.9 Four Channel LVDS Transmitter (for gmZAN3L Only) The gmZAN3L implements the industry standard flexible four channel LVDS transmitter. The LVDS transmitter can support the following: • ...
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Supported LVDS 24-bit Panel Data Mappings Table 17. Channel 0 R0, R1, R2, R3, R4, R5, G0 Channel 1 G1, G2, G3, G4, G5, B0, B1 Channel 2 B2, B3, B4, B5, PHS, PVS, PDE Channel 3 R6, R7, G6, ...
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OSD Position – The OSD menu can be positioned anywhere on the display region. The reference point is Horizontal and Vertical Display Background Start (DH_BKGND_START and DV_BKGND_START in Figure 21). OSD Stretch – The OSD image can be stretched horizontally ...
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... LUT is 64 colors by 16-bit in a RGB 5:5:5 format (bit 0 selectively enables blending with scaler data. 4.13 General Purpose Inputs and Outputs (GPIO’s) The gmZAN3 has general-purpose input/output (GPIO) pins for the gmZAN3L and five GPIO for the gmZAN3T. 4.14 Bootstrap Configuration Pins ...
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Host Interface Command Format – for 2 or 6-wire Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two nibbles respectively). These form an instruction byte, a device register address and/or one ...
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A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. A transfer is initiated (START high-to-low transition on HFS while HCLK is held high. A transfer is terminated by ...
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Figure ...
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Miscellaneous Functions 4.16.1 Low Power State The gmZAN3 provides a low power state in which the clocks to selected parts of the chip may be disabled (see Table 22) and the ADC powered-off. 4.16.2 Pulse Width Modulation (PWM) Back ...
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The following targeted specifications have been derived by simulation. 5.1 Preliminary DC Characteristics PARAMETER (1,2) 3.3V Supply Voltages (1.2) 1.8V Supply Voltages (1,2) Input Voltage (5V tolerant inputs) Input Voltage (non 5V tolerant inputs) Electrostatic Discharge Latch-up Ambient Operating Temperature ...
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... CYSNC/SOG is the only block turned on to detect Sync signals. (2) Includes pins CVDD_1.8, VDD_ADC_1.8 and VDD_RPLL_1.8. (3) Includes pins RVDD_3.3, AVDD_RED_3.3, AVDD_GREEN_3.3, AVDD_BLUE_3.3, AVDD_ADC_3.3, AVDD_3.3, AVDD_RPLL_3.3, AVDD_OUT_LV_3.3 and AVDD_LV_3.3. (4) XGA input at 85Hz with on/off pattern to XGA output operating at room temperature C0523-DAT-01G gmZAN3L DC Characteristics Table 22. SYMBOL MIN POWER (4) P XGA ...
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PARAMETER Power Consumption @ 95 MHz ACLK Power Consumption @ Low Power Mode 3.3V Supply Voltages (AVDD and RVDD) 1.8V Supply Voltages (VDD and CVDD) (1) Supply Current @ Low Power Mode Supply Current @ 95 MHz ACLK (2) • ...
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Preliminary AC Characteristics The following targeted specifications have been derived by simulation. All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating conditions used were 125 DIE Table 24. Clock Domain ...
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Microcontroller Interface Timing (Muxed Address/Data) for Register Read/Write Table 27. Parameter AD valid to ALE trailing edge setup time Trailing edge of ALE to AD hold time WR# leading edge to AD valid delay Trailing edge of WR ...
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asu Figure 31. Microcontroller Interface Timing (Muxed Address/Data) for Table 28. Parameter AD valid to ALE trailing edge setup time Trailing edge of ...
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... Figure 33. 6 Ordering Information Order Code Application gmZAN3T XGA with TTL Panel interface gmZAN3L XGA with single LVDS transmitter Panel interface C0523-DAT-01G ...
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Mechanical Specifications NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 do include mold mismatch and are determined at datum plane - Dimension b does not ...