MXT3010EP Mindspeed Technologies, MXT3010EP Datasheet
MXT3010EP
Related parts for MXT3010EP
MXT3010EP Summary of contents
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MXT3010 Reference Manual Version 4.1 Order Number: 100108-05 ...
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October 1999 Copyright (c) 1999 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the information can change without notice. Maker Communications, Inc. disclaims ...
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C ONTENTS Preface xxi Section 1 CHAPTER 1 CHAPTER 2 MXT3010 Reference Manual Maker Products xxi Using this manual xxiii Contacting Maker Support Services xxiv Changes Installed in This Version of the Manual xxv Subsystems 1 Introduction 3 MXT3010 features ...
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CHAPTER 3 CHAPTER 4 iv Instruction execution 13 Instruction space organization 14 Instruction cache 15 SWAN processor instruction classes 18 Arithmetic Logic Unit (ALU) instructions 19 Branch instructions 19 Registers 21 Flag registers 24 HEC generation and check circuit 25 ...
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CHAPTER 5 CHAPTER 6 CHAPTER 7 MXT3010 Reference Manual Mode 0 operation 53 Mode 1 operation 54 Bus contention avoidance 55 Fast Memory sequence diagrams 56 The Cell Buffer RAM 59 Internal cell storage in the Cell Buffer RAM 60 ...
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CHAPTER 8 Section 2 vi Post-increment option on rla operations 107 Data alignment 107 Byte manipulations on Port1 108 Post-DMA Operation Directives (PODs) 109 Burst and non-burst operation (Port2) 109 Port Operations 110 Port1 basic protocol 110 The Port1 control ...
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CHAPTER 9 CHAPTER 10 MXT3010 Reference Manual Registers 189 Register types 189 Software registers 189 Hardware registers 190 Specifying registers in SWAN instructions 190 Initializing software and hardware registers 191 R32 General Purpose - 0000 R33 General Purpose - FFFF ...
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CHAPTER 11 viii Triadic register 223 Immediate 224 Overflow flag 225 Instruction options 226 Modulo arithmetic 226 Automatic memory updates 228 ALU branching 228 ADD Add Registers 234 ADDI Add Register and Immediate 235 AND And Registers 236 ANDI And ...
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CHAPTER 12 CHAPTER 13 MXT3010 Reference Manual Introduction 262 Target address 262 Condition code (ESS Field) 263 The logical state identifier (S-Bit) 264 Committed slot instructions 264 The Conditional operator (C-bit) 265 Subroutine linking 268 Counter system operation 269 BF ...
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CHAPTER 14 CHAPTER 15 CHAPTER 16 x Load and Store Fast Memory Instructions 293 General information for Load and Store Fast Memory instructions 294 Introduction 294 Transfer size (the #HW field) 295 Fast Memory address (the rsa and rsb fields) ...
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... Pin Information 367 MXT3010EP pinout 368 MXT3010EP signal descriptions 369 MXT3010EP JTAG/PLL pin termination 377 MXT3010EP pin listing 378 I/O pad reference 381 Electrical Parameters 383 MXT3010EP maximum ratings and operating conditions 384 DC electrical characteristics 385 AC electrical characteristics 385 MXT3010EP power sequencing 386 xi ...
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... Mechanical and Thermal Information 395 MXT3010EP mechanical/thermal information 396 Acronyms 399 Device Initialization 401 Initializing the MXT3010EP 402 Downloading firmware 402 How the system determines the boot path 402 How the application uses the output pins 403 How the code set is structured 404 ...
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FIGURE 1. MXT3010 and surrounding system devices 5 FIGURE 2. SWAN processor address spaces and access instructions 11 FIGURE 3. SWAN instruction space 14 FIGURE 4. Formation of the page offset and the instruction tag 16 FIGURE 5. Target address ...
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... FIGURE 41. UTOPIA Port receive full timing - single PHY, 8-bit mode 95 FIGURE 42. UTOPIA Port transmit full timing - single PHY, 8-bit mode 95 FIGURE 43. DMA command queues for the MXT3010EP 100 FIGURE 44. Diagram of Port1 DMA instruction bits FIGURE 45. Port1 DMA Read transfer with a Wait state 119 FIGURE 46 ...
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... FIGURE 102.Port2 read timing 358 FIGURE 103.Port2 write timing 358 FIGURE 104.Timing of CIN_BUSY and COUT_RDY 359 FIGURE 105.MXT3010EP reset timing 361 FIGURE 106.Reset trailing edge timing 362 FIGURE 107.Reset timing circuit 363 FIGURE 108.MXT3010EP package/pin diagram 368 FIGURE 109.Generating a quiet VAA 392 MXT3010 Reference Manual xv ...
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... FIGURE 110.MXT3010EP decoupling capacitor location 393 FIGURE 111.MXT3010EP package/pin diagram - top view 396 FIGURE 112.MXT3010EP package/pin diagram - side view 397 xvi MXT3010 Reference Manual ...
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Table 1 SWAN processor instruction classes 18 Table 2 Methods of specifying the branch target field 21 Table 3 Hardware registers requiring one instruction delay 23 Table 4 Hardware registers requiring two instruction delays 24 Table 5 Scoreboard sectioning control ...
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Table 41 Accesses With Hardware and Software Swaps, 32-bit, 16-bit, and 8-bit 168 Table 42 Definitions of CIN_BUSY and COUT_RDY 178 Table 43 ICSI pins 180 Table 44 ICSO pins 181 Table 45 Hardware registers 184 Table 46 Alphabetical list ...
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... Input clock timing parameters 344 Table 85 Fast Memory timing for the Maker MXT3010EP 346 Table 86 UTOPIA timing for Maker MXT3010EP 349 Table 87 Delay of UTOPIA clocks relative to MXT3010EP internal clock (CLK) 350 Table 88 Port1 timing table 353 Table 89 Port2 timing table 357 Table 90 ...
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Table 126 Instruction summary 418 xx MXT3010 Reference Manual ...
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Preface Maker Products Integrated Maker Communications delivers a wide range of ATM solutions based on the MXT3010 cell processing engine and the MXT3020 Circuits circuit interface coprocessor. The MXT3010 is a high-perfor- mance programmable cell processor engine specifically designed to ...
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AAL1, AAL5, IMA, and cell relay. Development Maker Communications offers a full suite of development tools for the MXT3010 Cell Processor including Verilog ...
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Using this manual This section provides information on the conventions used within this manual. Typographical This document uses the following typographical conventions when describing features of the hardware and software, user- conventions machine interactions, and variables. • Commands appear in ...
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Terminology Common acronyms and abbreviations are defined in “Acro- nyms” on page 399 and not in the text. In addition, this manual uses the following term as defined: Packets refer to Local Area Network (LAN) information and frames refer to ...
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... XOR rather than OR. A typographic error (“3020” vs “3010”) in the description of 7. out-of-bag floor life in “MXT3010EP mechanical/thermal information” on page 396 has been corrected. The note that explains the enabling/disabling of “R54-R55 8. Programmable Interval Timer registers” on page 211 has been changed ...
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Version 4.1 MXT3010 Reference Manual ...
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Section 1 This section is composed of eight chapters. It provides an over- view of the MXT3010 ATM cell processing engine and its major functional subsystems. MXT3010 Reference Manual Subsystems Version 4.1 1 ...
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Version 4.1 MXT3010 Reference Manual ...
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Introduction CHAPTER 1 The MXT3010 is Maker Communication’s innovative, program- mable ATM cell processing engine. The MXT3010 is built around Maker Communication’s SWAN processor and specifically designed for use in high-speed ATM cell-processing applications. The MXT3010 delivers throughput at hard-wired ...
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Introduction MXT3010 features MXT3010-based systems are insulated against changes in ATM standards because firmware modifications can accommodate these changes. The MXT3010 can: • Scale across both performance and application ranges. • Run at speeds ranging from 1.5 Mb ...
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FIGURE 1. MXT3010 and surrounding system devices 16-bit bus Application Multi-purpose specific DMA (Port2 devices PHY or UTOPIA switch fabric Port Host Inter-chip Processor Signalling MXT3010 MXT3010 subsystems While the SWAN processor is the heart of the MXT3010, the device ...
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Introduction • The UTOPIA port that provides connection to an ATM net- work via a UTOPIA Level 2 Multi-PHY interface. • The Port1 and Port2 interfaces: Port1 is a high performance 32-bit DMA host system interface and Port2 is a ...
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The “Subsystems” section includes information on: • The SWAN processor • The Cell Scheduling System • The Fast Memory port • The Cell Buffer RAM • The UTOPIA port • The Port1 and Port2 interfaces • Interchip communications The “Register ...
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Introduction 8 Version 4.1 MXT3010 Reference Manual ...
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The SWAN Processor CHAPTER 2 Multi-purpose Data Stream DMA (Port2) UTOPIA Cell Stream Port Inter-chip SWAN Signalling The SWAN processor is used in network protocol processing applications. This chapter describes how the SWAN processor functions and provides functional descriptions of ...
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The SWAN Processor The SWAN advantage The SWAN processor was designed using Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) design techniques. By combining the high pipeline speeds of a RISC processor with the instruction set power ...
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DMA operations are dispatched with a single instruction, and those for Port1 include flexible CRC capabilities. • Load and Store instructions include indexing and byte- swapping capability. Address spaces The architecture of the SWAN processor, a big-endian design, provides ...
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The SWAN Processor The processor executes instructions in a four stage instruc- tion pipeline. The four stages -- Fetch, Decode, Execute and Store -- utilize scoreboarding and feedback to ensure proper operation, minimize stalls, and safeguard against illegal instruction sequences. ...
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SWAN. Since it is truly multi-ported, it provides very low latency access to all arbiters. See “Direct Memory Access Instructions” on page 283. On-Chip Cell Scheduling System Scoreboard RAM - 4. 2Kbytes The Cell Scheduling System uses an on-chip RAM ...
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The SWAN Processor Instruction space organization The SWAN supports an instruction space of 128K 32-bit instructions, which must be 4-byte aligned. The instruction space spans 32 Segments of 4K instructions each. Figure 3 shows the SWAN instruction space. FIGURE 3. ...
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Instruction cache The internal Instruction Cache is 2048 instructions. The cache is a direct-mapped cache, with each 32-bit entry having an inde- pendent 4-bit tag. There are no separate valid bits for the cache entries. At device initialization time, all ...
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The SWAN Processor FIGURE 4. Formation of the page offset and the instruction tag Program counter (17-bits) Note: The Instruction Offset is a word offset, as opposed to a byte offset. If the instruction tag matches the corresponding cache tag, ...
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Otherwise, stale cache entries prevent proper operation. The SWAN’s bootstrap program pre- loads a tag of 0xF into all cache entries at initialization rec- ommended that no cacheable code be placed at a ...
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The SWAN Processor Observing cached program flow When the processor is executing out of cache, it does not need to access Fast Memory. However, if Fast Memory is not being used, the MXT3010 presents the program counter address on the ...
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Arithmetic Logic Unit (ALU) instructions Basic ALU The SWAN processor instruction set includes a complete suite of arithmetic, logical, and shifting instructions implemented in a instructions high performance ALU. The format of a typical ALU instruction is shown below: ADD ...
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The SWAN Processor Branch instructions allow the programmer to specify condi- tional branching decisions which will alter the instruction exe- cution sequence. The branching decisions are based on the state of the MXT3010 subsystems, as indicated in the External State ...
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TABLE 2. Instruction Branch Immediate (BI) Branch Fast Memory Shadow Register (BF) Branch Register (BR) Note 1:The Fast Memory shadow register is loaded with the first halfword For a complete description of the three basic branch instructions and the versions ...
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The SWAN Processor FIGURE 6. Pipeline feedback Using the execution stage feedback facility, an ALU instruction that modifies a register can be followed immediately by another ALU instruction that accesses that same register. Using the stor- age stage feedback facility, ...
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When a Load (LD) instruction is issued, the destination reg- ister, rd, does not contain the requested data until one cycle after the LD instruction is decoded. When a Load Double (LDD) instruction is issued, the sec- ond destination register, ...
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The SWAN Processor Writes to the following hardware registers should be followed by at least two other instructions before the new information in the register is used: TABLE 4. Location R42-write R43-read R60 R62 R63 Flag registers Flag registers include ...
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HEC generation and check circuit The MXT3010 provides two HEC generation and checking methods: HEC generation and checking is provided in the UTOPIA 1. port. See “Receive cell flow” on page 77. For applications which do not use the UTOPIA ...
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The SWAN Processor LIMD r32 #first_two_bytes LIMD r33 #second_two_bytes NOP NOP NOP CMP r33, x The HEC result can be used directly in a transmitted cell, or compared to the fifth byte in a received cell. The NOP instruc- tions ...
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The Cell Scheduling System CHAPTER 3 Multi-purpose Data Stream DMA (Port2) UTOPIA Cell Stream Port Inter-chip SWAN Signalling The Cell Scheduling System (CSS traffic-shaping system that operates as a combination of algorithmic- and hardware- assisted functions. The SWAN ...
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The Cell Scheduling System ing traffic shaping as a combination of algorithmic- and hard- ware-assisted functions, the programmer has complete control over the traffic-shaping algorithms used. This chapter includes the following information: • How the Cell Scheduling System works • ...
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TABLE 5. Bits 13:12 To clarify the discussion which follows, it will be assumed that the Scoreboard contains only a single section of 16,384 bits/ entries. The Scoreboard and Connection ID table are maintained by the SWAN processor working with ...
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The Cell Scheduling System FIGURE 7. Connection ID entries Connection ID 145 Available Connection ID 47 Connection ID Table During the cell-scheduling process, status bits in the Scoreboard table summarize the assigned or available status of each Con- nection ID ...
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Data transmission - servicing and scheduling The data transmission process consists of two major steps: Servicing the Connection ID table to find entries represent- 1. ing assigned time slots that are scheduled for transmission on an established virtual circuit. Scheduling ...
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The Cell Scheduling System The POPC instruction is a dispatched instruction operating out- side of the CPU such that the SWAN processor does not stall while the cell scheduler executes the POPC instruction. The SWAN processor can determine when the ...
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PUSHC specifies a 16-bit Connection ID and a target loca- tion within the periodic container (Scoreboard). The cell scheduler responds to PUSHC by scanning the Scoreboard look- ing for the first available location at or after the targeted loca- ...
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The Cell Scheduling System FIGURE 8. Servicing and scheduling Connection ID 145 Available Connection ID 47 Connection ID 123 Connection ID 321 Available Connection ID Table In the example shown in Figure 8, the requested location was six entries away ...
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Using GCRA to The scheduling of cells on a per-connection basis is completely implementation dependent. For example, an implementation calculate time can use the Generic Cell Rate Algorithm slots ment and Limit ((GCRA(I,L)) to schedule cells on a VC. The ...
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The Cell Scheduling System an established CBR connection, the target time slot is the current time slot. Maintaining the currently assigned time slots ensures consistent CBR connection performance. For CBR connections, the inter-cell emission interval is not time varying and ...
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Pacing the transmission rate of cells The MXT3010 can pace the transmission rate of cells in either of two ways: • Back pressure through the UTOPIA port • Use of an external clock Back pressure When the back pressure method ...
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The Cell Scheduling System Advantages of The back pressure method is preferable when transmitting cells over an ATM transmission link, as the ATM transmission link each method must be kept full, and the transmission of idle cells is required. The ...
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The following instructions represent typical cell scheduling operation: POPC R10 @R7 BI $RDY ESS5/0 $RDY BI $SAC ESS4/1 $SAC LMFM R16 @R10/ R10 16HW LNK MXT3010 Reference Manual Programming the Cell Scheduling System If the UTOPIA Port Transmit queue is ...
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The Cell Scheduling System The SWAN processor uses the information stored in the Channel Descriptor to build or retrieve a cell for the VC SAR appli- cation that uses dynamic scheduling as part of the service rou- tine, ...
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The SWAN processor completes servicing the connection by incrementing the service address contained in R7, modulo the Connection ID table size. For example, the SWAN processor can use the Add Immediate (ADDI) instruction to add 0x0002 to the address contained ...
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The Cell Scheduling System The PUSHC/POPC instruction buffer The cell scheduler contains a two-deep PUSHC/POPC instruc- tion buffer. The SWAN processor can issue the following cell scheduling instructions without entering a stall condition: • A PUSHC or PUSHF followed by ...
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In POPF POPC, the Cell Scheduling System translates the target address into a Scoreboard bit position. The Cell Schedul- ing System copies the state of that bit into the Assigned Cell flag (see below), and clears the bit ...
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The Cell Scheduling System FIGURE 10.Connection ID table address generation 18 17 TABLE 6. Bits [0] [14:1] [18:15] The Connection ID table entry generates the Scoreboard address corresponding to the specified Connection ID table entry as fol- lows: FIGURE 11.Scoreboard ...
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Initializing the Scoreboard The SWAN processor clears the Scoreboard during its system initialization routine. The SWAN processor initializes the Score- board by executing POPF instructions to all of the locations in the Connection ID table. Once the SWAN processor has ...
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The Cell Scheduling System Supporting multiple Scoreboard sections As indicated in Table 5, “Scoreboard sectioning control,” on page 29, the MXT3010 supports multiple Connection ID tables/ Scoreboard sections. The device supports a maximum of: • Eight 2K Connection ID tables/Scoreboard ...
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The Fast Memory Interface CHAPTER 4 Multi-purpose Data Stream DMA (Port2) UTOPIA Cell Stream Port Inter-chip SWAN Signalling The Fast Memory port provides the SWAN processor and the Cell Scheduling System with low latency access to external Channel Descriptors, program ...
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The Fast Memory Interface ory controller provides a glue-less interface to synchronous, flow-through, burst-mode cache RAMs. The Samsung KM718B90 and compatible parts are examples of suitable RAMs. This chapter describes: • SWAN processor accesses to Fast Memory • Cell Scheduling ...
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LMFM rd @rsa/rsb #HW [LNK] The SWAN processor uses the #HW field to specify the number of halfwords to be fetched and the rsa and rsb fields to specify the Fast Memory byte address at which the transfer will begin. ...
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The Fast Memory Interface Additional information on the LNK option and memory updat- ing, including restrictions, appears in “Linking (the LNK bit)” on page 299 and following pages. Further Further information about the LMFM instruction is provided in “Load and ...
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CRC operations” on page 305. Further Further information about the SHFM and SRH instructions is provided in “Load and Store Fast Memory Instructions” on Information page 293. Examples of SHFM and SRH ...
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The Fast Memory Interface Fast Memory configurations This section describes these configuration features: • Memory sizes supported • RAM selection and configuration • Mode 0 operation for chips with single or multiple Chip Enable inputs • Mode 1 operation for ...
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RAM selection and configuration The MXT3010 supports the following RAM configurations: Memory Size 128K Bytes 32Kx32 256K Bytes 64Kx32 512K Bytes 128Kx32 512K Bytes 128Kx32 1M Byte 256Kx32 Mode 0 operation The MXT3010 provides two operation modes for the Fast ...
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The Fast Memory Interface FIGURE 15.Mode 0 design example MXT3010 Mode 1 operation In Mode 1 the MXT3010 drives 18 address bits and four inde- pendent byte enables to directly address 256K 32-bit words in each of two memory banks. ...
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FIGURE 16.Mode 1 design example MXT3010 When operating in Mode 1, the Chip Select pins are used as Fast Memory Address lines 19 and 18. FCS1_ = FADRS[19]. FCS0_ = FADRS[18] Bus contention avoidance The timing of the two output ...
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The Fast Memory Interface Fast Memory sequence diagrams This section shows sequence diagrams for the following Fast Memory operations: • Read operations, single bank (Figure 17 on page 56) • Write operations, single bank (Figure 18 on page 57) • ...
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FIGURE 18.Fast Memory write operations - single bank FADRS[17:2] FDATout[31:0] FDATin[31:0] FOE0_ FCS0_ FWE[3:0]_ FIGURE 19.Fast Memory reads and writes - back-to-back and dual bank CLK Read Read Bank 0 Bank 0 FADRS[17: FDATout[31:0] FDATin[31:0] D0 Driven by ...
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The Fast Memory Interface 58 Version 4.1 MXT3010 Reference Manual ...
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The Cell Buffer RAM CHAPTER 5 Multi-purpose Data Stream DMA (Port2) UTOPIA Cell Stream Port Inter-chip SWAN Signalling The MXT3010’s internal Cell Buffer RAM buffers cells in both the transmit and receive directions. The CPU and the DMA unit can ...
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The Cell Buffer RAM Internal cell storage in the Cell Buffer RAM To store cells, the Cell Buffer RAM is configured into a number of 64 byte blocks referred to as cell holders. During reception, cells are written into cell ...
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The minimum allocation for receive cell holders is two, the maximum is eight, and receiver cell holder addressing begins at location 0x0000. The minimum allocation for transmit cell hold- ers is two, the maximum is eight, and transmit cell holder ...
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The Cell Buffer RAM Cell fields Independent of the specific cell format used, certain fields (if provided) occupy certain positions. Figure 21 shows these fields, and Table 10 summarizes their functions. FIGURE 21.Cell fields defined 48 bytes TABLE 10. Cell ...
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Figure 22 compares the 52-byte and 56-byte cell formats. FIGURE 22.Receive cell organization: 52-byte and 56-byte cells 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0034 0x0036 0x0038 0x003A 0x003C 0x003E Figure 22 does not show the HEC byte, ...
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The Cell Buffer RAM In 52-byte mode, it precedes the ATM Header field, while in 56- byte mode, the four-byte User Header precedes the ATM Header, and the Receive Cell Status Word follows the last byte of the SAR PDU. ...
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Whether generated by a CPU instruction or a DMA controller, Bit [10] of the local address selects the access method of the Cell Buffer RAM. Bit Linear method In linear method accesses, the Cell Buffer RAM is ...
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The Cell Buffer RAM FIGURE 23.Gather method accesses Please note the restrictions on gather access in 56-byte mode (see “Receive Cell Status location” on page 63). For additional information, please see “Cell Buffer RAM accesses” on page 317. 66 0x0000 ...
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... Cell Buffer RAM access The MXT3010EP Cell Buffer RAM has five independent 16-bit ports, each capable of moving data at the internal clock fre- quency. The arrangement of data ports is shown in Figure 24. FIGURE 24.Cell Buffer RAM access Port1 Read UTOPIA Tx/ Port2 Read CPU Read ...
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The Cell Buffer RAM The Port1 write operation is not guaranteed to see the new val- ues of R4/R5. This is true because Store Double (STD) instruc- tions are retired in the Cell Buffer RAM at half the rate they ...
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The UTOPIA port CHAPTER 6 Multi-purpose Data Stream DMA UTOPIA Cell Stream Port Inter-chip SWAN Signalling The UTOPIA port implements the ATM Forum’s UTOPIA Level 1 and Level 2 protocol for interfacing ATM Layer devices, such as the MXT3010, to ...
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The UTOPIA port Multi-PHY device with ports. In compliance with the ATM Forum specification, the UTOPIA connection operates as the Master device. This chapter includes: • UTOPIA port interface overview • Receive cell flow • Transmit cell ...
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Operating modes The UTOPIA port can be configured to operate in bi-directional mode with an 8-bit Receive (Rx) data path and an 8-bit Transmit (Tx) data path unidirectional mode as either a 16-bit Transmitter or a 16-bit Receiver. ...
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The UTOPIA port Selecting transmit Transmit-only operation is selected by setting bits [3:1] of the UTOPIA Configuration register (R62) to zeroes, thus placing or receive mode the UTOPIA port receiver in reset mode. Receive-only opera- tion is selected by setting ...
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The MXT3010 generates a UTOPIA output clock for each of the transmit and receive interfaces based on the setting of the clock selection ...
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The UTOPIA port UTOPIA cell formats Two standard formats for cells are defined for UTOPIA inter- faces depending on the width of the data bus in use. Addition- ally, proprietary schemes may define arbitrary cell lengths and formats as long ...
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FIGURE 29.HEC-enabled 52-byte mode 52-byte cell 0x0000 Unused 0x0002 Receive Cell Status Word 0x0004 ATM Header bytes 0, 1 0x0006 ATM Header bytes 2, 3 0x0008 SAR PDU bytes 0, 1 0x000A SAR PDU bytes 2, 3 0x000C SAR PDU ...
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The UTOPIA port FIGURE 31.HEC-enabled 56-byte mode 56-byte cell 0x0000 User Header bytes 0, 1 0x0002 User Header bytes 2, 3 0x0004 ATM Header bytes 0, 1 0x0006 ATM Header bytes 2, 3 0x0008 SAR PDU bytes 0, 1 0x000A ...
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Receive cell flow The UTOPIA Receiver transfers cells from an external framing device into the Cell Buffer RAM. All cells received from the physical layer device are written into the Cell Buffer RAM. If HEC insertion and checking is enabled ...
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The UTOPIA port 78 A Receive Cell Status word is stored in Cell Buffer RAM at the completion of each receive cell. The format of the Receive Cell Status word is Reserved HE ...
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FIGURE 33.The RXBUSY counter Decrement Receiver Busy Counter (Cells in Cell Buffer RAM awaiting CPU Rx servicing) The RXBUSY counter Function The RXBUSY counter tracks the arrival of new cells in the Cell Buffer RAM awaiting CPU servicing. The device ...
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The UTOPIA port Decrementing 80 instruction (“BI Branch Immediate” on page 272) can specify a conditional branch to $RECV_CELL if ESS9 $RECV_CELL ESS9/1 In addition to the RXBUSY indication on ESS9, a receiver attention output of ...
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FIGURE 34.The RXFULL counter Decrement Receiver Busy Counter (Cells in Cell Buffer RAM awaiting CPU Rx servicing) to RXENB_ The RXFULL counter Function The RXFULL counter indicates to the DMA engines and the CPU that cells are in the Cell ...
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The UTOPIA port the RXFULL counter. If the MXT3010 can accept a cell and the PHY has a cell to send, the UTOPIA port enables the transfer by asserting the ATM layer Receiver Enable (RXENB_) output. Decrementing The Port 1/Port ...
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The UTOPIA port transfers cells from the Cell Buffer RAM beginning at location 0x0200. The UTOPIA transmitter reads successive cells from the Cell Buffer RAM. During device ini- tialization, the programmer can specify how many cells the UTOPIA transmitter should ...
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The UTOPIA port UTOPIA transmitter counters The UTOPIA transmitter contains two counters, TXBUSY and TXFULL, that track cells in the transmit section of the Cell Buffer RAM. Figure 35 on page 84 and Figure 36 on page 85 show how ...
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Incrementing Program execution can be accelerated if the DMA controller increments the TXBUSY counter after it reads data. This tech- nique requires the DMA command to specify a memory read operation with the POD option (see “Post-DMA Operation Directives (PODs)” ...
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The UTOPIA port The TXFULL counter Function The TXFULL counter tracks the number of cells that are avail- able in the Cell Buffer RAM for transmission. The CPU uses this counter to determine if space is available in the Cell ...
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Decrementing As the UTOPIA transmitter processes the last byte of a cell, the transmitter decrements the TXFULL counter. CRC10 generation and checking support The UTOPIA port can perform CRC10 generation and checking in support of AAL3/4, OAM cells, and RM ...
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... PHY devices that can be polled during a 52- clock cell time from 26 to 14. Thus PHY devices are used, more than one cell time is needed to poll them all. Refer to Application Note 20, “MXT3010EP UTOPIA Level 1 and Level 2 Interface Operation” for further infomration. 88 ...
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The use of bits [15:9] is best understood by considering the con- figurations shown in Figure 37 and Figure 38. FIGURE 37.Level 2 PHY configurations Note: While only transmit control signals (TX) signals are shown, a corresponding set of receive ...
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The UTOPIA port FIGURE 38.Mixed Level 1 and Level 2 PHY configuration Notes:1.While only transmit control signals (TX) are shown, a corre- The implementation shown has two logical PHYs. In this con- figuration, TX/RXCTRL[3] is used as TX/RXCLAV for the ...
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Receive Header Reduction hardware The MXT3010 provides receive header reduction via bits [6:0] of the System register (R63). The results of this reduction can be used as a Channel ID. The bit definitions are as follows: TABLE 16. Receive Header ...
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The UTOPIA port Receive header reduction mode is enabled by bit 0 of the UTOPIA Configuration register (R62). TABLE 17. Receive Header Reduction enable bit Bits 0 92 Description UTOPIA Receiver Reduction Mode Enable Bit 0 Reduction Function Disabled (ATM ...
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UTOPIA port configuration summary UTOPIA configuration information is stored in the UTOPIA Configuration register, R62. The SWAN processor passes this information to the UTOPIA Port at system initialization. Two bits (0,1) in the ESS register (R42) are also used in ...
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The UTOPIA port UTOPIA port sequence diagrams This section shows sequence diagrams for the following UTOPIA Port operations: • Receive timing for single PHY, 8-bit mode (Figure 39 on page 94) • Transmit timing for single PHY, 8-bit mode (Figure ...
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FIGURE 40.UTOPIA Port transmit timing - single PHY, 8-bit mode TxPeriod TXCLK TXSOC TXENB_ TXDATA[7:0] P48 TXCLAV FIGURE 41.UTOPIA Port receive full timing - single PHY, 8-bit mode RxPeriod RXCLK RXSOC RXENB_ RXDATA[7:0] P47 P48 Note 2 RXCLAV FIGURE 42.UTOPIA ...
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The UTOPIA port 96 Version 4.1 MXT3010 Reference Manual ...
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The Port1 and Port2 Interfaces CHAPTER 7 Application Multi-purpose Specific DMA (Port2) Devices PHY or UTOPIA Switch Port Fabric Inter-chip Host Signalling Port1 and Port2 are high-speed interface ports. For each port, this chapter includes: • Port interface overview • ...
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The Port1 and Port2 Interfaces Port interface overview Both Port1 and Port2 provide high speed transfer paths to and from the MXT3010 Cell Buffer RAM. The characteristics of the two ports differ, however, and are shown in Table 19. TABLE ...
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The transfer’s starting address in memory (from registers rsa and rsb) • The transfer’s starting address in the Cell Buffer RAM (from register rla) • The size of the transfer (from BC/#, BC/# value is specified, ...
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... Port1 and Port2 DMA command queues The Port1 and Port2 command queues each have two stages referred to as the queue stage and the active stage. Figure 43 shows the DMA command queues for the MXT3010. FIGURE 43.DMA command queues for the MXT3010EP 100 MXT3010 Processor Processor Command ...
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The DMA command information generated by a DMA read or write instruction is written into the selected SWAN command queue. The command is transferred into the associated DMA controller’s command queue as soon as the queue is available. If the ...
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The Port1 and Port2 Interfaces TABLE 20. ESS Bits for DMA Controller status ESS bit State Function TABLE 21. Example of DMA Controller status bit utilization ESS 13 & Branch instructions ...
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Port Controller features The Cyclical Redundancy Check 32 generator for Port1 A CRC32 generator is provided in the Port1 DMA Controller to generate and to check AAL5 CRC32 polynomials during seg- mentation and reassembly operations. The CRC32 circuit gener- ates ...
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The Port1 and Port2 Interfaces DMA transfer, read the CRC32 partial result from the selected partial result register and save those results in the Channel Descriptor to use the next time that a cell arrives. On transmits, for the last ...
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CRCX and CRCY At the time that a DMA read or write operation with CRCX or CRCY indicated is initiated to Port1, the MXT3010 automati- address holding cally stores the address contained in the internal Fast Memory registers Link Address ...
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The Port1 and Port2 Interfaces nary Port1 DMA transfer (see Figure 45 on page 119), but no P1QRQ_ or P1RQ_ signals are generated, the external arbiter does not manipulate P1ASEL_ or P1TRDY_, and data is not transferred on the Port1 ...
Page 133
Post-increment option on rla operations The target rla register can automatically increment when the DMA transfer is completed with the DMA Plus instruction. The increment is 64 modulo 512. If eight 64-byte Cell Buffer regis- ters are used, this saves ...
Page 134
The Port1 and Port2 Interfaces Byte manipulations on Port1 The Port1 bus supports only word and halfword DMA writes, with P1HWE [1:0] being used as selects for the half-words. However, the P1 address leads (P1AD [31:0]) provide a byte address, ...
Page 135
Post-DMA Operation Directives (PODs) The port DMA Controllers support a feature referred to as Post- DMA Operation Directives, or PODs. PODs instruct the DMA controller to perform UTOPIA port counter manipulations when the operation ends. For instance, during reassembly, firmware ...
Page 136
The Port1 and Port2 Interfaces transfers on a typical asynchronous multiplexed bus. Non-burst mode is used with low-speed non-synchronous transfer devices such as PHYs, CAMs, and FLASH memories. While Port1 supports only burst mode operations, Port2 sup- ports both burst ...
Page 137
FIGURE 44.Diagram of Port1 DMA instruction bits rsa rsb TABLE 24. Port 1 DMA instruction bit mapping Reg rsa rsb Port1 control signals Table 25 describes the signals ...
Page 138
The Port1 and Port2 Interfaces TABLE 25. Signals to control Port1 transfers Signal Purpose P1QRQ_ When the Port1 state machine detects the presence of a command in the queue stage of the Port1 DMA command queue, the state machine asserts ...
Page 139
... The Port1 control state machine General information concerning DMA transfers As indicated in “The Port DMA command queues” on page 100, the MXT3010EP asserts a port’s RQ_ signal if that port has a DMA command active. Additionally, it asserts the associated QRQ_ signal if there is an additional DMA command enqueued behind the active command. The port’ ...
Page 140
... Thus, in Table 26, IRDY_ is asserted only when P1AD is presenting In-Data. • END_ The END_ output is asserted by the MXT3010EP during the Last Transfer state. Although not shown in Table 26, the state machine also has a COMMSEL input. During DMA transfers, the COMMSEL sig- nal is low for all states shown. Please see“ ...
Page 141
... Data Read During a Data Read, an external device drives data onto the P1AD bus and the MXT3010EP reads that data. Thus, the P1AD column in the state table shows In-Data, and the IRDY_ column shows assertion (low) indicating that the MXT3010EP will read the data. There are three common ...
Page 142
... P1AD bus, but the MXT3010EP ignores that data. Thus, the P1AD column in the state table shows In-X, and the IRDY_ column shows de-assertion (high) indicating that the MXT3010EP will not read the data. There are three com- mon cases for what happens after a Data Wait: - ...
Page 143
Tri-state During a tri-state condition, all outputs are tri-state. This condition is always entered whenever ASEL_ is asserted (low) and TRDY_ is de-asserted (high). The state machine maintains separate versions of the tri-state condition depending upon the state from ...
Page 144
The Port1 and Port2 Interfaces TABLE 26. State table for the Port1 DMA burst read state machine Input Signals Current State Any Any pre Auto-turnaround Any post ...
Page 145
FIGURE 45.Port1 DMA Read transfer with a Wait state CLK P1QRQ_ P1RQ_ P1ASEL_ P1TRDY_ P1RD P1END_ P1ADin[31:0] P1ADout[31:0] P1HWE[1:0] P1IRDY_ COMMSEL LTN (Internal) State Next state is determined by table line # Figure 45 shows the Last Transfer (LTX) and ...
Page 146
... Data Read state. During Data Read, an external device places data on the P1AD leads, and the MXT3010EP asserts the IRDY_ lead low to indi- cate it is going to sample that data. Since ASEL_ is still high and TRDY_ is low, the state machine samples that condition, and line 9 of the state table causes the next state Data Read state ...
Page 147
... During Data Wait, the incoming data is ignored (“In-X”), and the IRDY_ lead goes high to indicate that the MXT3010EP is not going to sample the data. In the example, TRDY_ returns is returned to the low state, the state machine samples that condi- tion, and line 12 of the state table causes the next state Data Read state ...
Page 148
The Port1 and Port2 Interfaces FIGURE 46.Port1 DMA Read transfer without a Wait state CLK P1QRQ_ P1RQ_ P1ASEL_ P1TRDY_ P1RD P1END_ P1ADin[31:0] P1ADout[31:0] P1HWE[1:0] P1IRDY_ COMMSEL LTN (Internal) State Next state is determined by table line # Figure 46 is ...
Page 149
... Thus, in Table 27, IRDY_ is asserted only when the next state is Out-Data. • END The END_ output is asserted by the MXT3010EP during the Last Transfer state. This output can be used by any external logic that requires this information. Although not shown in Table 27, the state machine also has a COMMSEL input. During DMA transfers, the COMMSEL sig- nal is low for all states shown. Please see“ ...
Page 150
... The Port1 and Port2 Interfaces • Data Write During a Data Write, the MXT3010EP drives data onto the P1AD bus and an external device reads that data. Thus, the P1AD column in the state table shows Out-Data, and the IRDY_ column shows assertion (low) indicating that the MXT3010EP is sourcing valid data ...
Page 151
There are two other cases for what happens after a Data Wait, but these are used less often than the three listed above • Tri-state During a tri-state condition, all outputs are tri-state. This condition ...
Page 152
The Port1 and Port2 Interfaces TABLE 27. State table for the Port1 DMA burst write state machine Input Signals Current State Any Any Address ...
Page 153
FIGURE 47.Port1 DMA Write transfer with a Wait state CLK P1QRQ_ P1RQ_ P1ASEL_ P1TRDY_ P1RD P1END_ P1ADin[31:0] P1ADout[31:0] P1HWE[1:0] P1IRDY_ COMMSEL LTN (Internal) State Next state is determined by table line # Figure 47 shows the Last Transfer (LTX) and ...
Page 154
... Data Write. During Data Write, the MXT3010EP places data on the P1AD leads, and the MXT3010EP asserts the IRDY_ lead low to indi- cate that it has done so. Since ASEL_ is still high and TRDY_ is low, the state machine samples that condition, and line 5 of the state table causes the next state Data Write state ...
Page 155
... Data Write state. During Data Write, the MXT3010EP places data on the P1AD leads, and the MXT3010EP asserts the IRDY_ lead low to indi- cate that it has done so. Since ASEL_ is still high and TRDY_ is low, the state machine samples that condition, and line 5 of the state table causes the next state Data Write state ...
Page 156
The Port1 and Port2 Interfaces FIGURE 48.Port1 DMA Write transfer without a Wait state CLK P1QRQ_ P1RQ_ P1ASEL_ P1TRDY_ P1RD P1END_ P1ADin[31:0] P1ADout[31:0] P1HWE[1:0] P1IRDY_ COMMSEL LTN (Internal) State Next state is determined by table line # Figure 48 is ...
Page 157
Port1 reads and writes, photocopy Figure 49 and Figure 50 below, and cut them on the heavy lines shown. Paste them together to create the desired diagram. FIGURE 49.Cut-and-Paste Version of Port1 ...
Page 158
The Port1 and Port2 Interfaces FIGURE 50. Cut-and-Paste Version of Port1 Write CLK P1QRQ_ P1RQ_ P1ASEL_ P1TRDY_ P1RD P1END_ P1ADin[31:0] P1ADout[31:0] P1HWE[1:0] P1IRDY_ COMMSEL LTN (Internal) State Next state is determined by table line # 132 QRQ_ reasserts if another ...
Page 159
... TRDY_ (high) to bring the Port1 bus into a tri-state condition. The external logic then asserts the COMMSEL input of the MXT3010EP. The P1RD signal, driven by the external device, determines whether the I/O transfer is a read or write. Since the state tables for COMMSEL reads and COMMSEL writes are so brief, Table 28 shows the combined state table for both reads and writes ...
Page 160
... Clean Up state so that the Port1 state machine will enter the desired state after the Clean Up state COMMIN write, data is written from an external device into the MXT3010EP COM- MOUT read, data is read from the MXT3010EP by an external device. 134 ...
Page 161
... During the Tri-state condition, the external logic asserts the COMMSEL input and drives P1RD to select a read or write transfer. Detecting the assertion of COMMSEL, the MXT3010EP prepares an internal data path for the read or write of R40/41, the Host Communication registers. In Figure 51, the MXT3010EP samples the assertion of COM- MSEL high and P1RD low, and line 6 of the state table causes the next state to be Comm In Write ...
Page 162
... Comm Out Data Valid. During Comm Out Data Valid, data supplied by the concatenation of R40 and R41 within the MXT3010EP is supplied to the external device. If the external device can sample the data quickly during Comm Out Data Valid, the external logic can condition the states of ASEL_ (low), TRDY_ (high), and COMMSEL (low) such that line 1 of the state table causes the next state to be Tri-state ...
Page 163
Port2 basic protocol The Port2 interface supports two transfer mechanisms: MXT3010-initiated DMA burst mode transfers and non-burst transfers. Each command issued to the DMA command queue is tagged as either burst or non-burst, via rsa bit 7. If rsa[7] is ...
Page 164
The Port1 and Port2 Interfaces The information in Table 29 can also be expressed as shown in Table 30. TABLE 30. Another view of Port2 burst DMA instruction bit mapping Firmware Byte Address Bit A00 (lsb) A01 A02 A03 A04 ...
Page 165
Figure 53 and Table 31 illustrate the correspondence between rsa/rsb register values, the Port2 bus signals, and a logical half- word address for Port2 non-burst DMA transfers. FIGURE 53.Diagram of Port2 non-burst DMA instruction bits 15 rsa 15 rsb A1 ...
Page 166
The Port1 and Port2 Interfaces The information in Table 31 can also be expressed as shown in Table 32. TABLE 32. Another view of Port2 non-burst DMA instruction bit mapping Firmware Byte Address Bit A00 (lsb) A01 A02 A03 A04 ...
Page 167
Multi-function AI pins (P2AI[3:0]) In burst mode, P2AI [3:0] provide an address index consisting of the lower four bits of an address (see Table 29). In non-burst mode, P2AI[3:2] provide the most significant address bits (see Table 31). Also in ...
Page 168
The Port1 and Port2 Interfaces The Port2 control state machine Port2 DMA transfers originate and terminate as discussed in “General information concerning DMA transfers” on page 113. Port2 DMA burst-mode read transfers Table 34shows the state table for Port2 DMA ...
Page 169
TABLE 34. State table for the Port2 DMA burst-mode read state machine Input Signals Current State Any Any pre Auto-turnaround Any post Auto-turnaround Address ...
Page 170
The Port1 and Port2 Interfaces A sequence diagram for a typical DMA burst-mode read transfer using the Port2 read state table (Table 34) is shown in Figure 54. This diagram includes a wait state. FIGURE 54.Port2 DMA burst-mode Read transfer ...
Page 171
A second sequence diagram for a typical DMA burst-mode read transfer using the Port2 read state table (Table 34) is shown in Figure 55. This diagram does not include a wait state. FIGURE 55.Port2 DMA burst-mode Read transfer without a ...
Page 172
The Port1 and Port2 Interfaces Port2 DMA burst-mode write transfers Table 35 shows the state table for Port2 DMA burst-mode write transfers and Figure 56 shows a sequence diagram for a Port2 DMA burst-mode write transfer. Table 35 is identical ...
Page 173
TABLE 35. State table for the Port2 DMA burst write state machine Input Signals Current State Any Any Address Address ...
Page 174
The Port1 and Port2 Interfaces FIGURE 56.Port2 DMA burst-mode write transfer with a Wait state CLK P2QRQ_ P2RQ_ P2ASEL_ P2TRDY_ P2RD P2END_ P2ADin[15:0] P2ADout[15:0] P2AI[3:0] P2IRDY_ P2QBRST LTN (Internal) State Next state is determined by table line # The sequence ...
Page 175
A sequence diagram for a typical DMA burst-mode write trans- fer using Table 35 is shown in Figure 56. This diagram does not include a wait state. FIGURE 57.Port2 DMA burst-mode write transfer without a Wait state CLK P2QRQ_ P2RQ_ ...
Page 176
The Port1 and Port2 Interfaces Port2 DMA non-burst-mode read transfers Table 36shows the state table for Port2 DMA non-burst-mode read transfers and Figure 59 shows a sequence diagram for a Port2 DMA non-burst-mode read transfer. TABLE 36. State table for ...
Page 177
... P2AD leads. The Port2 DMA Read command can spec- ify, via bits [10:8] of the rsa register, the number of wait states that occur before the MXT3010EP samples the data. In the example shown above, 5 wait states have been inserted. Version 4.1 Port Operations ...
Page 178
The Port1 and Port2 Interfaces Prepare for another DMA transfer (having detected 1. P2QRQ_ asserted) Relinquish the bus by entering a tri-state condition 2. Perform some other type of bus operation 3. Having decided on the appropriate course of action, ...
Page 179
Expiration of the wait timer asserts LTN, and line 7 of the state table indicates the next state is Last Transfer (LTX). As with all of the other DMA transfer types discussed, Last Transfer is ...
Page 180
The Port1 and Port2 Interfaces Port2 DMA non-burst-mode write transfers Table 37shows the state table for Port2 DMA burst-mode write transfers and Figure 60 shows a sequence diagram for a Port2 DMA burst-mode read transfer. TABLE 37. State table for ...
Page 181
... LTN (Internal) State Next state is determined by table line # Note:During a Port2 Non-Burst DMA Write, the MXT3010EP places data The sequence of states shown in Figure 59 is exactly the same as that shown in Figure 58, except that this is a write. The same description applies, substituting writes for reads as necessary. ...
Page 182
The Port1 and Port2 Interfaces Additional Port1 and Port2 Design Information Arbitrating access to Port1 System configurations utilizing the MXT3010 often have a Host processor installed on Port1. This allows the Host processor to access the MXT3010 Communication I/O registers ...
Page 183
An existing DMA transfer should not be interrupted. The 3. maximum MXT3010/Memory transfer is 255 bytes (64 bus data cycles recommended that the maximum Host/ Memory transfer also be 64 bus data cycles. The Bus Controller may also ...
Page 184
... To prevent bus contention on shared port interface signals, port interface controllers should create a tri-state cycle between the times the MXT3010EP and another device drive the bus. In addition, to prevent the bus from floating indefinitely, port inter- face controllers must ensure the bus is driven when there is no device performing transfers on the bus ...
Page 185
When the MXT3010 is the only Port2 Master, the device may be parked on the bus. Parking minimizes bus handshaking over- head. While the MXT3010 is parked, it actively drives the P2AD pins bus parking configuration, P2TRDY_ may ...
Page 186
The Port1 and Port2 Interfaces fer may be ignored if the transfer desired an odd byte size, but the last byte transfer will be written. Thus, the number of data cycles for four bytes may be one or two bus ...
Page 187
Transfer complete A DMA transfer can conclude for either of two reasons: • The byte count (BC/#) has reached zero • The P1ABORT_ signal has been asserted (Port1 only) Byte Count zero Standard end For both Port1 and Port2, END_ ...
Page 188
The Port1 and Port2 Interfaces Early end option Mode bits (bit 6 and bit 7) in the Mode Configuration register (R42) enable an early end option for each port. When enabled, the End signal asserts concurrent with the request for ...
Page 189
External DMA cycle abort (P1ABORT_) The MXT3010 has an input signal (P1ABORT_) that permits an external device to indicate an early termination of a DMA read operation from Port1 memory. During a DMA Read operation on Port1, assertion of the ...
Page 190
The Port1 and Port2 Interfaces Endian-ness Within modern computer systems, there are two ways of addressing a multi-byte data value such as (hex) ABCD: FIGURE 64.Most Significant Byte is the Lowest Address (“Big-endian”) Data: Address: FIGURE 65. Least Significant Byte ...
Page 191
TABLE 38. Comparison of Big-endian and Little-endian Read Operations Access 32-bit 16-bit xxx0 16-bit xxx2 byte xxx0 byte xxx1 byte xxx2 byte xxx3 A convenient method of dealing with this problem is to use the swapping instructions available in little-endian ...
Page 192
The Port1 and Port2 Interfaces FIGURE 67.Word Access A 0 Hardware D 3 Software A 3 The combination of hardware and software shown in Figure 67 produces the same result as shown in Table 38 on page 165, the first ...
Page 193
FIGURE 68.16-bit xxx0 Access A 0 Hardware D 3 Software 3 FIGURE 69. 16-bit xxx2 Access A 0 Hardware D 3 Software C 3 The combinations of hardware and software shown in Figures 68 and 69 produce Table 40. MXT3010 ...
Page 194
The Port1 and Port2 Interfaces TABLE 40. Accesses With Hardware and Software Swaps, 32-bit and 16-bit Access Big-Endian Result 32-bit ABCD 16-bit xxx0 AB 16-bit xxx2 CD FIGURE 70.Byte Access A 0 Hardware D 3 The combination of hardware and ...
Page 195
... Also, the MSC controls the resetting and boot loading of the MXT3010EP through a 128 Kbyte boot PROM. MXT3010 Reference Manual Port1 and Port2 Reference Designs Version 4 ...
Page 196
... MXT3010EP COMMIN/COMMOUT register and the PCI host. The CINBUSY, COUTRDY, and COMMSEL sig- nals are connected to the P1MemMaker. Typically the PCI host communicates to code running in the MXT3010EP via commands passed through the MXT3010EP’s COMMIN register. The code running in the MXT3010EP communi- cates to the PCI host via commands passed through the MXT3010EP’ ...
Page 197
This module defines the data paths. • dram_cntrl.v This module defines the DRAM controller. • p1orca.v This module defines the top level of P1MemMaker • p1ctrl.v This module defines the Port 1 A/B controller. • pci_be.v This module ...
Page 198
... In Maker’s MXT3025 evaluation Board and similar designs, Maker uses P2MemMaker, a device that is a integrated memory system con- troller, a PCI interface, and an MXT3010EP Port2 interface. It performs the following functions: • Memory System Controller The Memory System Controller (MSC) provides the bus arbitration and selection functions for the PCI or Port2 access for tranfers to shared memory ...
Page 199
... MXT3010EP Port2 address space. The MSC supports full speed burst tranfers up to 256 bytes to the memory system, but transfers must not cross 4- Kbyte boundaries. The MSC also controls transfers to the non-burst memory space. • PCI Interface The PCI Bus interface is a 32-bit, 33 Mhz PCI Version 2 ...
Page 200
The Port1 and Port2 Interfaces This module defines the Port 2 Rx/Tx controller. Endian Several Maker products utilize the Port2 MemMaker FPGA to allow the MXT3010 and a PCI bus to share a Port2 memory. Implementation in Within the Port2 ...