ACD80800 ETC-unknow, ACD80800 Datasheet
ACD80800
Related parts for ACD80800
ACD80800 Summary of contents
Page 1
... Data Sheet: ACD80800 Address Resolution Logic (8K MAC Addresses) Please check ACD’s website for update information before starting a design Web site: http://www.acdcorp.com/tech.html ACD Confidential Material For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission. Rev.1.0.0.E Last Update: September 19, 2000 or Contact ACD at: Email: support@acdcorp ...
Page 2
CONTENT LIST 1. SUMMARY 2. FEATURES 3. FUNCTIONAL DESCRIPTION 4. PIN DESCRIPTION 5. INTERFACE DESCRIPTION 6. REGISTER DESCRIPTION 7. COMMAND DESCRIPTION 8. TIMING DESCRIPTION 9. ELECTRICAL SPECIFICATION 10. PACKAGING 2 ...
Page 3
... Together with the non-blocking architecture of the ACD’s switch controllers, the chip set (a ACD switch controller plus the ACD80800, plus ACD80900 in a managed switch system) can provide wire speed forwarding rate under any type of traffic load. Figure-1: ACD80800 Used in A Managed n-Port Fast Ethernet Switch System P(n-1) P(n-2) P(n-3) ACD82xxx ...
Page 4
... Interface contains the signals of the data bus and the state bus. By snooping the data bus and the state bus of ACD’s switch controller, ACD80800 can detect the occurrence of any destination MAC address and source MAC address embedded inside each frame. ...
Page 5
... CPU through the UART data output line. CPU Interface Registers ACD80800 provides a bunch of registers for the control CPU. Through the registers, the CPU can read all ad- dress entries of the address table, delete particular ad- dresses from the table, add particular addresses into ...
Page 6
... PIN DESCRIPTIONS Figure-3: Pin Diagram Of ACD80800 (The ARL Chip ...
Page 7
Pin Table Pin Name Description 1 GND Ground WDI63 Data from s witch controller chip. 3. WDI62 Data from s witch controller chip. 3. WDI61 Data from s witch controller chip. 3. ...
Page 8
... SWDIR is a 2-bit signal to indicate the direction of the data displayed on the SWDI bus, 01 for receiving, 10 for transmitting for other states. ACD80800 only deals with the received data. SWSTAT bus is a 4-bit signal, used to indicate the mean- ing (status) of the data. The 4-bit status is defined as: ...
Page 9
... ACD80800 active to the nCPUOE or nCPUWE signals. CPUIRQ is used to generate an interrupt request to the CPU. For each source of the interrupt, refer to the de- scription of the interrupt source register ...
Page 10
... PosCfg0 21 PosCfg1 The DataRegX are registers used to pass the param- eter of the command to the ACD80800, and the result of the command to the CPU. The AddrRegX are registers used to specify the address associated with the command. The CmdReg is used to pass the type of command to the ACD80800 ...
Page 11
... NOCPU , 0 for have a control CPU, 1 for do not have a control CPU. Note: When NOCPU is set as 0, ACD80800 will not start the initialization process until a System Start command is sent to the command register. The PosCfgReg1 is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin ...
Page 12
CPU to send the System Start command before the initialization process can be started. bit 5:3 - UARTID, shared with CPUD5:CPUD3, 3-bit ID for UART communication. 7. COMMAND DESCRIPTION Command 09H Description: Add the specified MAC address ...
Page 13
Valid - 1 indicates the entry is a valid one. Rsvd - Reserved bits. Command 11H Description: Read next entry of address book. Parameter: None Result: The result is indicated by the Result register. ...
Page 14
MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 50H Description: Read first locked entry. Parameter: ...
Page 15
Figure-4: Format of a 48-bit MAC Address in a Data Register Command FFH Description: System reset. Parameter: None Result: ...
Page 16
TIMING DESCRIPTIONS Figure-5: Timing Of CPU Read Operation HIGH Time t1 Read cycle time t2 Address access time t3 Output hold time t4 ...
Page 17
Figure-6: Timing Of CPU Write Operation Time Description t1 Write Cycle Time t2 Address Valid to Write End t3 Address Hold for Write ...
Page 18
ELECTRICAL SPECIFICATION Absolute Maximum Ratings Operation at absolute maximum ratings is not implied exposure to stresses outside those listed could cause permanent damage to the device. DC Supply voltage : VDD DC input current: Iin DC input voltage: Vin ...
Page 19
PACKAGING Symble Min Nom Max 0.25 0.33 na ...