EDR2518ABSE-8C-E Elpida Memory, Inc., EDR2518ABSE-8C-E Datasheet
EDR2518ABSE-8C-E
Available stocks
Related parts for EDR2518ABSE-8C-E
EDR2518ABSE-8C-E Summary of contents
Page 1
... PRELIMINARY DATA SHEET 288M bits Direct Rambus DRAM EDR2518ABSE (512K words 18 bits 32s banks) Description Features ) ...
Page 2
... R: RDRAM Density & Bit Organization 2518: 288M (x18 bit) Voltage, Interface A: 2.5V, RSL 2 Package SE: FBGA ( BGA with back cover) Die Rev. Preliminary Data Sheet EDR2518ABSE Environment Code Blank: Sn-Pb Solder E: Lead Free Speed AEP: 1066MHz (tRAC= 32ns, tDAC= 3clocks) AE: 1066MHz (tRAC= 32ns) AD: 1066MHz ...
Page 3
... CTMN CTM ROW2 ROW0 COL3 COL1 DQB1 CFM CFMN ROW1 COL4 COL2 COL0 DQB0 GND V GND GND DD GND DD REF Preliminary Data Sheet EDR2518ABSE ...
Page 4
... Row access control. Three pins containing control and address information for row accesses. 5 Column access control. Five pins containing control and address information for column accesses. 9 Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. 80 Preliminary Data Sheet EDR2518ABSE ...
Page 5
... Bank 0 Bank 1 Bank 2 • • • Bank 13 Bank 14 Bank 15 Bank 16 Bank 17 Bank 18 • • • Bank 29 Bank 30 Bank 31 Preliminary Data Sheet EDR2518ABSE RQ4..RQ0 or COL4..COL0 DQA8..DQA0 5 9 RCLK 1:8 Demux Packet Decode COLC COLM COP ...
Page 6
... Electrical Characteristics .................................................................................................................................... 58 29. Timing Characteristics ........................................................................................................................................ 58 30. RSL Clocking ....................................................................................................................................................... 59 31. RSL - Receive Timing .......................................................................................................................................... 60 32. RSL - Transmit Timing......................................................................................................................................... 61 33. CMOS - Receive Timing....................................................................................................................................... 62 34. CMOS - Transmit Timing ..................................................................................................................................... 64 35. RSL - Domain Crossing Window ........................................................................................................................ 65 36. Timing Parameters .............................................................................................................................................. 66 37. Absolute Maximum Ratings................................................................................................................................ 67 6 CONTENTS Preliminary Data Sheet EDR2518ABSE ...
Page 7
... I - Supply Current Profile ................................................................................................................................. 67 DD 39. Capacitance and Inductance .............................................................................................................................. 68 40. Interleaved Device Mode ..................................................................................................................................... 70 41. Glossary of Terms ............................................................................................................................................... 74 42. Package Drawing ................................................................................................................................................. 76 43. Recommended Soldering Conditions................................................................................................................ 77 Preliminary Data Sheet EDR2518ABSE 7 ...
Page 8
... General Description The figure on page block diagram of the EDR2518ABSE. It consists of two major blocks : a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core 2.1 GB/s. ...
Page 9
... These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge. Preliminary Data Sheet EDR2518ABSE 9 ...
Page 10
... DX4..DX0 Device address for COLX packet. BX4..BX0 Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drivers 0's). XOP4..XOP0 Opcode field for COLX packet. Specifies precharge control, and power management functions. OL Preliminary Data Sheet EDR2518ABSE ...
Page 11
... DQA8..0 C1 DQB8.. CTM/CFM Note2 COL4 DX4 XOP4 RsvB BX1 S=1 COL3 M=0 DX3 XOP3 BX4 BX0 COL2 DX2 XOP2 BX3 COL1 DX1 XOP1 BX2 COL0 DX0 XOP0 EDR2518ABSE ROP8ROP5 ROP2 ROP10 ROWR Packet ...
Page 12
... Move this device into the attention (ATTN) power state (see Figure 23-1). 000 RLXR Move this device into the standby (STBY) power state (see Figure 23-2). 001 TCAL Temperature calibrate this device (see figure 25-2). 010 TCEN Temperature calibrate/enable this device (see Figure 25-2). 000 NOROP No operation. Preliminary Data Sheet EDR2518ABSE ...
Page 13
... No operation. No operation. Precharge bank BX4..BX0 of this device (see Figure 12-2). Calibrate (drive) I current for this device (see Figure 25-1). OL current for this device (see Figure 25-1). OL Move this device into the standby (STBY) power state (see Figure 23-2). Reserved, no operation. Preliminary Data Sheet EDR2518ABSE 13 ...
Page 14
... This gap on the COL pins must be inserted by the controller CAC CAC CWD ••• ••• (b1) ••• after the COLC packet) is available to be used as an COLX RTR Preliminary Data Sheet EDR2518ABSE -t ) will automatically appear CWD CYCLE ...
Page 15
... DA8 DQA7 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 • • • DQA1 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 DQA0 DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63 MA0 MA1 EDR2518ABSE ...
Page 16
... Transaction a: ROPa a0 = {Da,Ba,Ra} Transaction b: ROPb b0= {Db,Bb,Rb} restriction applies to the same device with non-adjacent RR to the next ACT). RP for the sense amp and bank to precharge before RP applies, since the same device is addressed Preliminary Data Sheet EDR2518ABSE which depends upon the packet ...
Page 17
... PACKET x..x t PACKET x..x t RAS x..x t RAS xxxx x..x t PACKET t PACKET x.. Ba+1 is precharged/activated. PACKET RP x.. Ba-1 is precharged/activated. PACKET RP x.. x.. xxxx x..x t PACKET x.. x.. x.. EDR2518ABSE Example Figure 10-2 Figure 10-2 Figure 10-1 Figure 10-1 Figure 10-2 Figure 10-2 Figure 10-1 Figure 13-1 Figure 10-3 Figure 10-3 Figure 10-1 Figure 10-1 Figure 10-3 Figure 10-3 Figure 10-3 Figure 10-3 17 ...
Page 18
... RCDELAY ROPa a0 COPb b1 Transaction a: ROPa a0 = {Da,Ba,Ra} Transaction b: COPb b1= {Db,Bb,Cb1 xxxx == Da xxxx == Da /= {Ba, Ba+1, Ba- {Ba+1, Ba- {Ba} xxxx == Da xxxx == Da /= {Ba, Ba+1, Ba- {Ba+1, Ba-1} Preliminary Data Sheet EDR2518ABSE which RCDELAY Cb1 t Example RCDELAY x..x 0 x..x 0 x..x 0 x..x Illegal x..x t Figure 13-1 RCD x..x 0 x..x 0 x..x 0 x..x Illegal ...
Page 19
... Db Bb Cb1 WR xxxxx x.. Cb1 x.. Cb1 x.. Cb1 x.. Cb1 x.. Cb1 x..x Preliminary Data Sheet EDR2518ABSE COPc {Da,Ba,Ca1} ...
Page 20
... Bb Rb x..x xxxxx xxxxx x..x x.. xxxxx x..x x.. {Ba, Ba+1, Ba-1} x..x ACT == Da == {Ba} x..x ACT == Da == {Ba+1, Ba-1} x..x PRER == Da == {Ba, Ba+1, Ba-1} x..x PRER == Da == {Ba, Ba+1, Ba-1} x..x PRER == Da == {Ba, Ba+1, Ba-1} x..x NOROP xxxxx xxxxx x..x Preliminary Data Sheet EDR2518ABSE CRDELAY ROPb b0 a1= {Da,Ba,Ca1} b0= {Db,Bb,Rb} t Example ...
Page 21
... ACT a0 ACT c0 ACT PACKET Preliminary Data Sheet EDR2518ABSE a0 = {Da,Ba,Ra} RR7 a1 = {Da,Ba+1} RR3 b0 = {Da,Ba+1,Rb} RR4 b0 = {Da,Ba,Rb} RR11 b0 = {Da,Ba+1,Rb} RR12 b0 = {Da,Ba,Rb ...
Page 22
... PRER c0 PRER PACKET PP to complete. The hidden restore operation requires the RCD,MIN to complete. RP,MIN Preliminary Data Sheet EDR2518ABSE apart unless PACKET a0 = {Da,Ba,Ra} RR13 b0 = {Db,Bb,Rb} RR14 c0 = {Da,Bc,Rc} RR15 c0 = {Da,Ba,Rc} RR16 c0 = {Da,Ba+1Rc} RR9 b0 = {Db,Bb,Rb} RR10 c0 = {Da,Bc,Rc ...
Page 23
... PRER from the COLC packet that causes the OFFP after the COLC packet with the WR command RTR Preliminary Data Sheet EDR2518ABSE a0 = {Da,Ba,Ra {Da,Ba {Da,Ba,Rb ...
Page 24
... PRER a5 t OFFP PREX a5 Q (a1) Q (a2) Q (a3 {Da,Ba,Ra {Da,Ba,Ca1 {Da,Ba,Ca2 {Da,Ba,Ca3 {Da,Ba,Ca4} Preliminary Data Sheet EDR2518ABSE ...
Page 25
... RC PRER RAS RDP Q (a1) Q (a2) t CAC t CAC a1 = {Da,Ba,Ca1 {Da,Ba,Ca2} Preliminary Data Sheet EDR2518ABSE CYCLE ACT b0 ...
Page 26
... RC PRER RAS retire (a1) retire (a2) RTP MSK (a1) MSK (a2 RTR RTR D (a1) D (a2 CWD t CWD a1 = {Da,Ba,Ca1 {Da,Ba,Ca2} Preliminary Data Sheet EDR2518ABSE interval is RCD RTP ...
Page 27
... CTM/CFM This RD gets the old data ROW2 ..ROW0 COL4 retire (a1) MSK (a1) ..COL0 t RTR DQA8..0 DQB8..0 t CWD Transaction a: WR Transaction b: RD Transaction c: RD Preliminary Data Sheet EDR2518ABSE later. This CWD later RTR ...
Page 28
... RC PRER RAS RTR D (a1) Q (b1 CWD CAC a1 = {Da,Ba,Ca1 {Da,Ba {Da,Bb,Cb2} b3= {Da,Bb,Cb3 {Da,Bb,Cb5 {Da,Bb,Cb6} Preliminary Data Sheet EDR2518ABSE ...
Page 29
... MSK (b2) MSK (c1) t CWD D (z2) D (a1) D (a2) D (b1) D (b2 {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2 {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2 {Da,Ba,Ca1} a2= {Da,Ba,Ca2 {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2 {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2 {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2 {Da,Ba,Ce1} e2= {Da,Ba,Ce2 {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2} Preliminary Data Sheet EDR2518ABSE ...
Page 30
... CAC Q (z1) Q (z2) Q (a1) Q (a2) Q (b1 {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2 {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2 {Da,Ba,Ra {Da,Ba,Ca1} a2= {Da,Ba,Ca2 {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2 {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2 {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2 {Da,Ba,Re {Da,Ba,Ce1} e2= {Da,Ba,Ce2 {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2} Preliminary Data Sheet EDR2518ABSE ...
Page 31
... MSK (b1) MSK (b2) Q (z1) Q (z2) Q (a1) Q (a2) D (b1) D (b2 {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2 {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2 {Da,Ba,Ca1} a2= {Da,Ba,Ca2 {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2 {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2 {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2 {Da,Ba,Ce1} e2= {Da,Ba,Ce2 {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2} Preliminary Data Sheet EDR2518ABSE ...
Page 32
... SIO 1 from SIO0 to SIO1 SRQ - SRD command 00000000...00000000 00000000...00000000 addressed RDRAM devices 0/SD15..SD0/0 on SIO0 SA SINT SA SINT Preliminary Data Sheet EDR2518ABSE next transaction 1 00000000...00000000 1111 0 1 SINT 0 1 SINT ...
Page 33
... SDEV2 SA2 SD9 14 SDEV1 SA1 SD8 15 SDEV0 SA0 delay until next command. SCYCLE , 2816 t ) must be inserted between a SETR/CLRR command pair. SCYCLE CYCLE Preliminary Data Sheet EDR2518ABSE 00000000...00000000 The packet is repeated from SIO0 to SIO1 1 0 SIO0 or SIO0 or SIO1 ...
Page 34
... RDRAM device is from the ASIC component on the SIO bus (the closest RDRAM device is address 0 00000000...00000000 00001100 0000000000000000 The packet is repeated from SIO0 to SIO1 0000000000000000 of the CTM clock (for Channel and RDRAM devices) CYCLE Preliminary Data Sheet EDR2518ABSE ...
Page 35
... Each RDRAM device is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM device to a particular read domain. Preliminary Data Sheet EDR2518ABSE parameter for the system. The t RCD RCD ...
Page 36
... RP,MIN RC,MIN RCD,MIN RR,MIN RDRAM timing parameter that are present in the system. The REF,MAX RDRAM timing parameter that are present in the system. CCTRL,MAX RDRAM timing parameter that are present in the system. The TEMP,MAX Preliminary Data Sheet EDR2518ABSE , and t RDRAM timing PP,MIN ...
Page 37
... The behavior of EDR2518ABSE at initialization is as follows distinguished by the "S28IECO" bit in the SPD. S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match ...
Page 38
... Asymmetry control. Controls asymmetry of V NAP exit. Specifies length of NAP exit phase A. NAP exit. Specifies length of NAP exit phase A + phase B. DQ select. Selects CMD framing for NAP/PDN exit. PDN exit. Specifies length of PDN exit phase A. Preliminary Data Sheet EDR2518ABSE /V swing for DQA swing for DQB ...
Page 39
... Test register. Write with zero after SIO reset. Test register. Do not read or write after SIO reset. Test register. Do not read or write after SIO reset. t core parameter. Determines t parameters. (Version 3 only) CPS-C OFFP Vendor-specific test registers. Do not read or write after SIO reset. EDR2518ABSE parameters. 39 ...
Page 40
... See Figure 23-3 and Timing conditions table. 40 Figure 22-1 Control Registers (1/7) Address : 021 NSR SRP PSX 0 SDEVID4..0 Address : 023 MVER5..0=mmmmmm DBL1 ) CPS Preliminary Data Sheet EDR2518ABSE Reset value REFBIT2..0=101 ...
Page 41
... Figure 22-1 Control Registers (2/7) Address : 024 CORG4..0=01000 SPT0 DEVTYP2..0=000 Address : 022 Address : 040 DEVID4..0 Preliminary Data Sheet EDR2518ABSE BYTB ...
Page 42
... Address : 044 ASYM 0 CCB6.. voltage swing about the V reference voltage for the OL OH REF output current for the DQB8..DQB0 pins. OL Preliminary Data Sheet EDR2518ABSE Reset value Reset value Reset value ...
Page 43
... NAPX4..0 NAPXA4..0 0.5 cycles, 1 1.5 cycles) between the CMD pin +t , NAPXB MAX Address : 046 PDNXA12..0 Address : 047 PDNX12.. SCYCLE PDNXB MAX Preliminary Data Sheet EDR2518ABSE timing window will ...
Page 44
... CYCLE Address : 049 units. This value must be greater than or equal to the t CYCLE CYCLE Preliminary Data Sheet EDR2518ABSE TCAL ) CYCLE ). =2. =1.875 ns CAC CYCLE 8 t Note CYCLE CYCLE not allowed CYCLE 9 t CYCLE ...
Page 45
... Address : 04b Address : 04c TCYCLE13..0 datasheet parameter in 64ps units. For the t CYCLE,MIN ” (39 64ps). 16 Preliminary Data Sheet EDR2518ABSE TCDLY1 later for the four CYCLE 2.50 ns (2500ps), this field 45 ...
Page 46
... This adds a programmable delay to t CYCLE ) through “11” Refer to the Figure 22-1 (5/7). CYCLE CYCLE Preliminary Data Sheet EDR2518ABSE Reset value TCPS This field OFFP. ...
Page 47
... Attention state. Ready for ROW and COL packets. ATTNW Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. Preliminary Data Sheet EDR2518ABSE Blocks consuming power Self-refresh or REFA-refresh TCLK/RCLK-Nap REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver REFA-refresh ...
Page 48
... RLX - RLX command in ROWR,COLC,COLX packets SIO0 - SIO0 input value SETR/CLRR PDEV.CMD - (PDEV=DEVID)•(CMD=01) ATTN - ROWA packet(non-broadcast) or ROWR packet (non-broadcast) with ATTN command must periodically return to ATTN or STBY. NLIMIT Preliminary Data Sheet EDR2518ABSE pins. during which SA after the ROW packet, the CYCLE ...
Page 49
... COP a0 restricted COP a1 ..COL0 XOP a0 XOP a1 DQA8..0 DQB8..0 t ASP Power Note NAP ATTN/STBY State after the PDNR command. CD Preliminary Data Sheet EDR2518ABSE ROP=non-broadcast ROWA or ROWR/ATTN a0={d0, b0, r0} a1={d1, b1, c1} No COL packets may be placed in the three indicated positions; i.e. at (TFRM-{1,2,3})• ...
Page 50
... This RDRAM device may not re-exit NAP state for The RDRAM device enters PDN state at the end of cycle T PU0 . The equations for these two parameters depend upon a number PU1 Preliminary Data Sheet EDR2518ABSE . NU0 . The RDRAM device may 3 13 ...
Page 51
... SCK PDN exit CMD NU1 no entry to NAP or PDN no exit no exit t =5•t +(2+256•PDNX)•t CYCLE PU0 t =8•t - (0.5•t if NSR=0 PU1 CYCLE =23•t if NSR=1 CYCLE EDR2518ABSE ...
Page 52
... RR to address c0, the same bank (or an adjacent bank) as the RC after the initial REFA command in order to precharge RAS parameter. After PDN or NAP (when self-refresh is BURST Preliminary Data Sheet EDR2518ABSE REF interval, the banks may be BURST ...
Page 53
... BURST restricted ROP ROP COP COP restricted XOP XOP (NAPX •t )/(256•PDNX•t SCYCLE STBY Note 2 EDR2518ABSE ...
Page 54
... TEMP t TCQUIET No read data from devices being calibrated Preliminary Data Sheet EDR2518ABSE output current in OL /N, where N CCTRL ...
Page 55
... V CYCLE REF t =1.875ns V CYCLE REF Note2 t =2.50ns V CYCLE REF t =1.875ns V CYCLE REF ) DIL – 0.3 V CMOS Preliminary Data Sheet EDR2518ABSE MIN. MAX. Unit — 100 C 2.50 + 0.13 V — 2.0 % –2.0 +2.0 % 2.50 + 0.25 V 1.80 + 0.2 V 1.80 + 0.1 V 1.40 + 0.2 V – 0.5 V – 0.2 V REF – 0.5 V – 0.15 V REF + 0 ...
Page 56
... CYCLE =2.50ns 1.0 CYCLE t =1.875ns 1.0 CYCLE 5.5 –1 Note4 100 7 — — CYCLE — 150 2 140 — — Preliminary Data Sheet EDR2518ABSE MAX. Unit Figures 3.33 ns Figure 30-1 2.5 0.5 ns Figure 30-1 60% t Figure 30-1 CYCLE 1.0 Figure 22-1 1.0 t Figure 30-1 CYCLE +0.1 Figure 30-1 +0.1 t Figure 35-1 CYCLE 0.65 ns Figure 31-1 0.45 ns — ns Figure 31-1 — ...
Page 57
... Notes Figure 23-4 Preliminary Data Sheet EDR2518ABSE 57 ...
Page 58
... CYCLE t = 2.50 ns 0.2 CYCLE t = 1.875 ns 0.2 CYCLE — = 20pF (SD read data hold) 2 — — LOAD,MAX — — — — — — — — Preliminary Data Sheet EDR2518ABSE MAX. Unit 0.5 C/Watt +10 µA +10 µ 2.0 mA — 30.6 mA 30.1 mA +10.0 µA 0.3 V – 0.3 — V MAX ...
Page 59
... CH CYCLE and t parameters are measured from falling to rising and rising Preliminary Data Sheet EDR2518ABSE parameter is measured from the V CIH 80% 50% 20% V CIL CIH 80% 50% 20% V CIL ...
Page 60
... COL 60 interval. The set/hold window of the sample points is t CYCLE voltage point of the input transition. REF V CM 0.5•t CYCLE odd even t DF Preliminary Data Sheet EDR2518ABSE /t . The CIH 80% 50% 20% V CIL V DIH 80% V REF 20% V DIL ...
Page 61
... CTM CTMN 0.75•t CYCLE DQA t QR DQB and t . The t parameters are measured at the 50 % voltage Q,MIN Q,MAX 0.75•t CYCLE 0.25•t CYCLE Q,MAX Q,MAX Q,MIN odd even t QF Preliminary Data Sheet EDR2518ABSE V CIH 80% 50% 20% V CIL t Q,MIN V QH 80% 50% 20 ...
Page 62
... The set/hold window of the sample points t CYCLE1 t t CH1 CL1 odd even DF2 Preliminary Data Sheet EDR2518ABSE and t , all measured at the CH1 CL1 V IH,CMOS 80% 50% 20% V IL,CMOS V IH,CMOS 80% 50% 20% V IL,CMOS V IH,CMOS 80% 50% ...
Page 63
... SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals are measured at the V level. REF Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit SCK DQA[5: PDEV Preliminary Data Sheet EDR2518ABSE /t around the rising edge IH,CMOS 80% 50% 20% V IL,CMOS V ...
Page 64
... Figure 34-1 CMOS Timing - Data Signals for Transmit SCK t Q1,MAX SIO0 t QF1 SIO0 or SIO1 t t DF1 PROP1,MAX SIO0 or SIO1 t QF1 64 t HR,MIN t QR1 t DR1 t PROP1,MIN Preliminary Data Sheet EDR2518ABSE /t . The SCK Q1,MIN Q1,MAX and t , measured at QR1 QF1 V IH,CMOS 80% 50% 20% V IL,CMOS V OH,CMOS 80% 50% 20% V OL,CMOS V IH,CMOS 80% 50% 20% V ...
Page 65
... CAC TR ••• CAC CAC TR CYCLE ••• CAC CAC TR CYCLE Preliminary Data Sheet EDR2518ABSE is needed in order to DCW value. TR (cases A CYCLE , the command to DCW,MAX This is shown CAC TR CYCLE t CYCLE Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) ...
Page 66
... RCD OFFP Preliminary Data Sheet EDR2518ABSE MAX. Units Figures PC800 -8C (-40) 28 — t Figure13-1 CYCLE Figure14 Figure13-1 CYCLE Note Figure14-1 8 — t Figure13-1 CYCLE Figure14-1 8 — t Figure10-3 CYCLE 8 — ...
Page 67
... The RDRAM device dissipates logic one is driven. Parameter MIN. –0.3 –0.5 – MIN. CYCLE 2.50 ns/1.875 ns 2.50 ns/1.875 ns 2.50 ns 1.875 ns 2.50 ns 1.875 ns 2.50 ns 1.875 ns CYCLE 2.50 ns 1.875 ns Note 2 . Preliminary Data Sheet EDR2518ABSE MAX. Unit +100 C MAX. Unit 6 100 130 ...
Page 68
... I I pin), the effective inductance must be defined DD assumes a loop with the RSL pin adjacent ground DQA,DQB,RQ Pin GND Pin L I CTM,CTMN, CFM,CFMN Pin GND Pin L I,CMOS SCK,CMD Pin GND Pin L I,CMOS SIO0,SIO1 Pin GND Pin Preliminary Data Sheet EDR2518ABSE ...
Page 69
... Note This value is a combination of the device IO circuitry and package capacitances. MIN. 1066 MHz – 800 MHz – – – – Note 1066 MHz 2.0 800 MHz 2.0 – – 1066 MHz 4 800 MHz 4 MIN. – Note 1.7 Note – Preliminary Data Sheet EDR2518ABSE MAX. Unit 3.5 pF 4.0 0.2 nH 0.6 nH 1.8 nH 2.3 pF 2.4 0 MAX. Unit 8 ...
Page 70
... Interleaved Device Mode 70 Preliminary Data Sheet EDR2518ABSE ...
Page 71
... DQB4 DQB3 DQB2 notation • • • • • • • • • • • • • banks) bank (2 rows) row (2 dualocts) EDR2518ABSE RDRAM 6 RDRAM 7 00110 00111 same as same as device 0 device 0 DQA1 DQA0 DQB1 DQB0 dualoct (144 bits) one bit 71 ...
Page 72
... DQA1 DQA0 DQA3 DQB6 DQB1 DQB0 DQB3 DQB8 DQA7 DQA0 DQA1 DQA2 DQB7 DQB0 DQB1 DQB2 DQA8 Preliminary Data Sheet EDR2518ABSE 111 Mapping for previous figure DQA0 DQB0 CTM/CFM DQA0 DQA1 DQA1 DQB1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 ...
Page 73
... DQA2 DQA5 DQA4 DQA7 DQB2 DQB5 DQB4 DQB7 DQA8 DQA3 DQA4 DQA5 DQA6 DQB3 DQB4 DQB5 DQB6 DQB8 Preliminary Data Sheet EDR2518ABSE 111 DQA4 DQB4 CTM/CFM DQA0 DQA5 DQA1 DQB5 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 DQB1 DQB2 DQB3 ...
Page 74
... Control register – PDN exit delay B. pin efficiency The fraction of non-idle cycles on a pin. PRE PREC, PRER, PREX precharge commands. PREC Precharge command in COP field. precharge Prepares sense amp and bank for activate. OL PRER Precharge command in ROP field. Preliminary Data Sheet EDR2518ABSE ...
Page 75
... INIT register field – Serial device ID. self-refresh Refresh mode for PDN and NAP. sense amp Fast storage that holds copy of bank’s row. Preliminary Data Sheet EDR2518ABSE SETF Set fast clock command from SOP field. SETR Set reset command from SOP field. SINT Serial interval packet for control register read/write transactions ...
Page 76
... Package Drawing 80-ball FBGA ( BGA) 0 10.2 ± 0.1 INDEX MARK 17.16 ± 0.10 0.1 S 1.2 1.9 B INDEX MARK 76 0 0.2 S 1.13 max. S 0.35 ± 0.05 0.8 1.1 1.78 0.8 A 0.4 80- 0.45 ± 0.05 0. Preliminary Data Sheet EDR2518ABSE Unit: mm ECA-TS2-0089-01 ...
Page 77
... Recommended Soldering Conditions Please consult our sales office for soldering conditions of the Type of Surface Mount Device . Preliminary Data Sheet EDR2518ABSE 77 ...
Page 78
... ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. 78 Preliminary Data Sheet EDR2518ABSE CME0107 ...
Page 79
... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. EDR2518ABSE M01E0107 ...