SAA6703AH/V1 INTEGRATED CIRCUIT SOLUTION, SAA6703AH/V1 Datasheet

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SAA6703AH/V1

Manufacturer Part Number
SAA6703AH/V1
Description
CMOS Single Chip 8 Bit Microcontroller with 16 kByte of Flash
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet

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SAA6703AH/V1
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PHI
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240
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
IS89C54/58/64
FEATURES
• 80C52 based architecture
• 16K/32K/64K Byte Flash Memory with fast-
• 256 x 8 RAM
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
• Program memory lock
• Power save modes:
• Eight interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Packages available:
Integrated Circuit Solution Inc.
MC009-0B
IS89C54/58/64
CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
with 16/32/64-Kbytes of FLASH
pulse programming algorithm
– 64K Program Memory and 64K Data Memory
– Lock bits (3)
– Idle and power-down
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
GENERAL DESCRIPTION
embedded microcontroller family. The IS89C54/58/64 uses
the same powerful instruction set, has the same architecture,
and is pin-to-pin compatible with standard 80C52 controller
devices. IS89C54/58/64 are just changed internal Flash
size, other features are same as standard IS89C52.
a 256 x 8 RAM; 32 I/O lines for either multi-processor
communications; I/O expansion or full duplex UART; three
16-bit timers/counters; an eight-source, two-priority-level,
nested interrupt structure; and on chip oscillator and clock
circuit. The IS89C54/58/64 can be expanded using standard
TTL compatible memory.
Figure 1. IS89C54/58/64 Pin Configuration: 40-pin DIP
IS89C54, IS89C58, IS89C64 are members of
The IS89C54/58/64 contains a 16K/32K/64K x 8 Flash;
T2EX/P1.1
INT0/P3.2
INT1/P3.3
RxD/P3.0
TxD/P3.1
WR/P3.6
RD/P3.7
T2/P1.0
T0/P3.4
T1/P3.5
XTAL2
XTAL1
GND
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
ICSI
1

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SAA6703AH/V1 Summary of contents

Page 1

... ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. ...

Page 2

... RxD/P3 TxD/P3.1 13 INT0/P3.2 14 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 Figure 2. IS89C54/58/64 Pin Configuration: 44-pin PLCC TOP VIEW P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VPP ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 Integrated Circuit Solution Inc. MC009-0B ...

Page 3

... IS89C54/58/64 P1.5 1 P1.6 2 P1.7 3 RST 4 RxD/P3 TxD/P3.1 7 INT0/P3.2 8 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 Figure 3. IS89C54/58/64 Pin Configuration: 44-pin PQFP Integrated Circuit Solution Inc. MC009- P0.4/AD4 P0.5/AD5 32 31 P0.6/AD6 30 P0.7/AD7 29 EA/Vpp 29 NC ALE/PROG 27 26 PSEN P2.7/A15 ...

Page 4

... IS89C54/58/64 16K/32K/64K MAIN CODE FLASH VCC VSS P2[7:0] P0[7:0] PORT 1 P1[7:0] 4 SFR BLOCK 80C31 CPU CORE TIMER 2 UART INT0 TIMER 0 Figure 4. IS89C54/58/64 Block Diagram 256 BYTE RAM ALE PSEN RST CLOCK EA & TIMING XTAL2 XTAL1 INT1 PORT 3 TIMER 1 P3[7:0] Integrated Circuit Solution Inc. MC009-0B ...

Page 5

... P1.0-P1.7 1-8 2 P2.0-P2.7 21-28 24-31 Integrated Circuit Solution Inc. MC009-0B PQFP I/O Name and Function Address Latch Enable: Output pulse for latching the low byte 27 I/O of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking ...

Page 6

... Crystal 1: Input to the inverting oscillator amplifier and input the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Ground: 0V reference Power Supply: This is the power supply voltage for operation Integrated Circuit Solution Inc. MC009-0B ...

Page 7

... Dummy Address 3 Lock Bits Falsh Cell IS89C54 Figure 5. The Flash Architecture of IS89C54/58/64 Integrated Circuit Solution Inc. MC009-0B MEMORY MAP AND REGISTERS Table 1 shows program memory and data memory size versus three products. The IS89C54/58/64 series includes a standard IS80C32 and a 16K/32K/64K Flash Memory ...

Page 8

... IS89C54/58/64 will enter received command mode. The flash command is accepted by the flash command decoder in command received mode. The programming interface is listed in figure 6. P1 VCC P2.5-2.0 P3.3-3.2 P0 RST H PSEN L P3.4 P3.5 ALE/PROG P2.6 P2.7 EA/VPP P3.6 VSS P3.7 VCC 10K D7-D0 Ready/Busy Timeout P2.6 P2.7 P3.6 P3.7 Integrated Circuit Solution Inc. MC009-0B ...

Page 9

... VPP value, code value FFH respects to 12V and 55H respects to 5V. Table 4. Signature Bytes Information Addr 30H IS89C54 (VPP=12V) D5H IS89C54 (VPP=5V) D5H IS89C58 (VPP=12V) D5H IS89C58 (VPP=5V) D5H IS89C64 (VPP=12V) D5H IS89C64 (VPP=5V) D5H Integrated Circuit Solution Inc. MC009-0B P2.6 P2.7 P3 12V 12V/H ...

Page 10

... If the output is low (Busy), the device erasing/programming state with an internal verification. If the output is high, the device is ready to read data. While the RY/BY signal is at low level (Busy) and Timeout is high level, the programming or erasing procedure is failed. Integrated Circuit Solution Inc. MC009-0B ...

Page 11

... U Same as 3, also external execution is disabled Integrated Circuit Solution Inc. MC009-0B 1. Set RST to high and PSEN to low. 2. Raise EA High (either 12V or 5V). 3. Read the “Read Signature Bytes” command to ensure the correct programming algorithm. 4. Verify that the memory blocks for programming are in the erased state, FFH ...

Page 12

... Operating Range Commercial devices case temperature VCC supply voltage Oscillator frequency Operating ranges define those limits between which the functionality of the device is guaranteed. 12 Rating Unit 0 to +70 °C (1) -65 to +125 °C -2.0 to +7.0 V (2) 1 +70 °C +4.5 to 5 MHz Integrated Circuit Solution Inc. MC009-0B ...

Page 13

... If I exceeds the test condition Pins are not guaranteed to sink greater than the listed test conditions. 2.The Icc test conditions are shown below. Minimum VCC for Power Down Integrated Circuit Solution Inc. MC009-0B Test conditions Iol = 100 µ 1.6 mA ...

Page 14

... Min Max — 20 — 26 — 32 — 38 — 50 — 62 — 5 — 6 — 7.6 — 9 — 12 — 15 — 50 Vcc Icc RST Vcc P0 NC XTAL2 XTAL1 EA GND Figure 8. Active Mode Vcc Integrated Circuit Solution Inc. Unit µA Vcc MC009-0B ...

Page 15

... Data valid to WR transition t QVWX Data hold after WR t WHQX RD low to address float t RLAZ high to ALE high t WHLH Integrated Circuit Solution Inc. MC009-0B t CLCX 0.7Vcc 0.2Vcc — 0.1 t CHCL t CLCL Tests in Active and Idle Mode (t CC =0V; C1 for port 0, ALE and PSEN Outputs=100pF; C1 for other outputs=80pF) ...

Page 16

... Min 3 — — Variable Oscillator (3.5-40 MHz) Min Max Unit –10 12t +10 ns CLCL CLCL –10 — ns CLCL –10 — ns CLCL 0 — ns — 10t ns CLCL Max Unit 40 MHz — ns — Integrated Circuit Solution Inc. MC009-0B ...

Page 17

... Busy# Low to Timeout High while Block 1 Erase (IS89C54) tBLTHE2 Busy# Low to Timeout High while Block 1 Erase (IS89C58) tBLTHE3 Busy# Low to Timeout High while Block 1 Erase (IS89C64) tBLTHE4 Busy# Low to Timeout High while Block 2 Erase (IS89C64) Integrated Circuit Solution Inc. MC009-0B Min Max Unit 11.5 12 ...

Page 18

... INSTR IN t LLIV t AVIV A15-A8 t LLDV t t LLWL RLRH t RLAZ t RLDV t LLAX t RHDX DATA IN t AVWL t AVDV A15-A8 FROM DPH Figure 12. External Data Memory Read Cycle t PXIZ A7-A0 A15-A8 t WHLH t RHDZ A7-A0 FROM PCL INSTR IN A15-A8 FROM PCH Integrated Circuit Solution Inc. MC009-0B ...

Page 19

... A7-A0 FROM RI OR DPL PORT 2 0 INSTRUCTION ALE CLOCK t QVXH DATA OUT t XHDV DATA IN Figure 14. Shift Register Mode Timing Waveform Integrated Circuit Solution Inc. MC009- LLWL WLWH t QVWX t LLAX DATA OUT t AVWL A15-A8 FROM DPH Figure 13. External Data Memory Write Cycle ...

Page 20

... IS89C54/58/64 P3[7:6] P2[7:6] P3[3:2] P2[5:0] P1[7:0] P0[7-0] VPP PROG VCC Figure 15. Read Signature bytes Timing(Arming Command) 20 00H t CVQV 30H 31H t t AVQV AVQV D5H 04H/08H/10H t WSCV 32H t AVQV 05H/FFH Integrated Circuit Solution Inc. MC009-0B ...

Page 21

... Lock bits verification. 3. Address don’t care while lock bits’ programming or verification. 4. Data don’t care while lock bits’ programming. Integrated Circuit Solution Inc. MC009-0B 0EH (1) ...

Page 22

... Lock bits verification. 22 01H/02H/04H ( BLCX t t CVPL BLPH t t PLBL BLBHE t BLBHEn t SHPL t t PLTL BLTHE t BLTHEn Figure 17. Erasing Timing 0CH/0DH ( SLCV CQCV CXQX Valid Address ( AVQV AXQX Valid Data t BHSL Integrated Circuit Solution Inc. MC009-0B ...

Page 23

... Note: 1.AC inputs during testing are driven at Vcc-0.5v for logic “1” and 0.45V for logic “0”. Timing measurements are made at Vih min for logic “1” and max for logic “0”. Integrated Circuit Solution Inc. MC009-0B 1st stage test mode ...

Page 24

... PLCC 600mil DIP PQFP Integrated Circuit Solution Inc. HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. HEADQUARTER: TH ROAD, MC009-0B ...

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