MT28F800B5WG-8B Micron Semiconductor Products, MT28F800B5WG-8B Datasheet

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MT28F800B5WG-8B

Manufacturer Part Number
MT28F800B5WG-8B
Description
1Meg x 8; 5V only, dula supply, smart 5 boot block flash memory
Manufacturer
Micron Semiconductor Products
Datasheet

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FLASH MEMORY
FEATURES
• Eleven erase blocks:
• Eight main memory blocks
• Smart 5 technology (B5):
• Advanced 0.18µm CMOS floating-gate process
• Compatible with 0.3µm Smart 5 device
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP and SOP packaging options
• Byte- or word-wide READ and WRITE
Notes:
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
OPTIONS
• Timing
• Configurations
• Boot Block Starting Word Address
• Operating Temperature Range
• Packages
80ns
1 Meg x 8
512K x 16/1 Meg x 8
Top
Bottom
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
MT28F008B5
Plastic 40-pin TSOP Type I
MT28F800B5
Plastic 48-pin TSOP Type I
Plastic 44-pin SOP (600 mil)
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
5V ±10% V
5V ±10% V
(MT28F800B5, 1 Meg x 8/512K x 16)
(10mm x 29mm)
(12mm x 20mm)
production programming
1. This generation of devices does not support 12V V
2. Contact factory for availability.
compatibility production programming; however, 5V
V
with no loss of performance.
PP
application production programming can be used
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE .
MT28F800B5WG-8 BET
CC
PP
Part Number Example:
application/
1
MARKING
MT28F008B5
MT28F800B5
None
WG
SG
VG
ET
-8
T
B
2
SMART 5 BOOT BLOCK FLASH MEMORY
PP
1
GENERAL DESCRIPTION
are nonvolatile, electrically block-erasable (Flash),
programmable
8,388,608 bits organized as 524,288 words (16 bits) or
1,048,576 bytes (8 bits). Writing or erasing the device is
done with a 5V V
performed with a 5V V
advances, 5V V
duction programming. These devices are fabricated
with Micron’s advanced 0.18µm CMOS floating-gate
process.
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
or overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code
implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
flash) for the latest data sheet.
MT28F008B5
MT28F800B5
5V Only, Dual Supply (Smart 5)
0.18µm Process Technology
40-Pin TSOP Type I
The MT28F008B5 (x8) and MT28F800B5 (x16/x8)
The MT28F008B5 and MT28F800B5 are organized
Please refer to Micron’s Web site
Micron Technology, Inc. Reserves the right to change products or specifications without notice.
PP
read-only
PP
is optimal for application and pro-
44-Pin SOP
voltage, while all operations are
CC
. Due to process technology
48-Pin TSOP Type I
memories
2
(www.micron.com/
©2002, Micron Technology Inc.
containing
8Mb

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MT28F800B5WG-8B Summary of contents

Page 1

... PP with no loss of performance. 2. Contact factory for availability. Part Number Example: MT28F800B5WG-8 BET 8Mb Smart 5 Boot Block Flash Memory MT28F800B5_3.fm - Rev. 3, Pub. 8/2002 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE . SMART 5 BOOT BLOCK FLASH MEMORY ...

Page 2

... Order Number and Part Marking MT28F800B5WG-8 B MT28F800B5WG-8 T MT28F800B5WG-8 BET MT28F800B5WG-8 TET Notes: 1. Contact factory for availability. 8Mb Smart 5 Boot Block Flash Memory MT28F800B5_3.fm - Rev. 3, Pub. 8/2002 SMART 5 BOOT BLOCK FLASH MEMORY Pin Assignment (Top View) 48 A16 47 BYTE ...

Page 3

X - Decoder/Block Erase Control 8Mb Smart 5 Boot Block Flash Memory MT28F800B5_3.fm - Rev. 3, Pub. 8/2002 SMART 5 BOOT BLOCK FLASH MEMORY MUX Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 8Mb ...

Page 4

PIN DESCRIPTIONS 40-PIN 48-PIN 44-PIN SOP TSOP TSOP NUMBERS NUMBERS NUMBERS – – 47 11, 10 21, 20, 19, 25, 24 ...

Page 5

TRUTH TABLE (MT28F800B5) FUNCTION RP# H Standby L RESET READ H READ (word mode) H READ (byte mode) Output Disable H WRITE/ERASE (EXCEPT BOOT BLOCK) ERASE SETUP H 3 ERASE CONFIRM H WRITE SETUP WRITE (word mode) ...

Page 6

TRUTH TABLE (MT28F008B5) FUNCTION Standby RESET READ READ Output Disable WRITE/ERASE (EXCEPT BOOT BLOCK) ERASE SETUP 3 ERASE CONFIRM WRITE SETUP 4 WRITE 5 READ ARRAY 2 WRITE/ERASE (BOOT BLOCK) ERASE SETUP 3 ERASE CONFIRM 3, 6 ERASE CONFIRM WRITE ...

Page 7

FUNCTIONAL DESCRIPTION The MT28F800B5 and MT28F008B5 Flash memo- ries incorporate a number of features ideally suited for system firmware. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. ...

Page 8

V status, write status, and erase status. Command Execution Cell (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read ...

Page 9

Parameter Blocks The two 8KB parameter blocks store less sensitive and more frequently changing system parameters and also may store configuration or diagnostic coding. These blocks are enabled for erasure when the super-voltage unlock ...

Page 10

INPUT OPERATIONS The DQ pins are used either to input data to the array or to input a command to the CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the ...

Page 11

COMMAND SET To simplify writing of the memory blocks, the MT28F800B5 and MT28F008B5 incorporate an ISM that controls all internal algorithms for writing and erasing the floating gate memory cells. An 8-bit com- mand set is used to control the ...

Page 12

COMMAND EXECUTION Commands are issued to bring the device into dif- ferent operational modes. Each mode allows specific operations to be performed. Several modes require a sequence of commands to be written before they are reached. The following section describes ...

Page 13

ERASE Sequence Executing an ERASE sequence sets all bits within a block to logic 1. The command sequence necessary to execute an ERASE is similar to that of a WRITE. To pro- vide added security against accidental block erasure, two ...

Page 14

WRITE/ERASE CYCLE ENDURANCE The MT28F800B5 and MT28F008B5 are designed and fabricated to meet advanced firmware storage requirements. To ensure this level of reliability, V must ±10% during WRITE or ERASE cycles. Due to process technology advances, 5V ...

Page 15

SELF-TIMED WRITE SEQUENCE (WORD OR BYTE WRITE) Start WRITE 40h or 10h WRITE Word or Byte Address/Data STATUS REGISTER READ SR7 = 1? YES Complete Status Check (optional) WRITE Complete Notes: 1. Sequence may be repeated ...

Page 16

SELF-TIMED BLOCK ERASE SEQUENCE Start WRITE 20h WRITE D0h, Block Address STATUS REGISTER READ NO SR7 = 1? Suspend ERASE? YES 2 Complete Status Check (optional) 3 ERASE Complete Notes: 1. Sequence may be repeated to ...

Page 17

Smart 5 Boot Block Flash Memory MT28F800B5_3.fm - Rev. 3, Pub. 8/2002 SMART 5 BOOT BLOCK FLASH MEMORY ERASE SUSPEND/RESUME SEQUENCE Start (ERASE in progress) WRITE B0h (ERASE SUSPEND STATUS REGISTER READ NO SR7 = ...

Page 18

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply Relative Input Voltage Relative to V ................... -0. Voltage Relative V .....................-0. RP Pin Voltage Relative to Vss... -0.5V to +12.6V Temperature Under ...

Page 19

CAPACITANCE (T = +25º MHz) A PARAMETER/CONDITION Input Capacitance Output Capacitance READ AND STANDBY CURRENT DRAIN Commercial Temperature (0ºC PARAMETER/CONDITION READ CURRENT: WORD-WIDE, TTL INPUT LEVELS (CE OE ...

Page 20

READ TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Commercial Temperature (0ºC AC CHARACTERISTICS PARAMETER Read cycle time Access time from CE# Access time from OE# Access time from address RP# HIGH to output valid delay OE# or CE# ...

Page 21

AC TEST CONDITIONS Input pulse levels ...................................... 0.4V to 2.4V Input rise and fall times.......................................<10ns Input timing reference level .................... 0.8V and 2V Output timing reference level ................. 0.8V and 2V Output load........................1 TTL gate and A0–A18/(A19) ...

Page 22

V IH A0–A18/(A19 DQ0–DQ7 DQ8–DQ14 RP TIMING PARAMETERS Commercial Temperature (0ºC ...

Page 23

RECOMMENDED DC WRITE/ERASE CONDITIONS Commercial Temperature (0ºC PARAMETER/CONDITION V WRITE/ERASE lockout voltage PP V voltage during WRITE/ERASE operation PP Boot block unlock voltage V WRITE/ERASE lockout voltage CC WRITE/ERASE CURRENT DRAIN Commercial Temperature (0ºC PARAMETER/CONDITION WORD WRITE CURRENT: V SUPPLY ...

Page 24

SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE#- (CE#-)CONTROLLED WRITES Commercial Temperature (0ºC AC CHARACTERISTICS PARAMETER WRITE cycle time WE# (CE#) HIGH pulse width WE# (CE#) pulse width Address setup time to WE# (CE#) HIGH Address hold ...

Page 25

V IH A0–A18/(A19) Note DQ0–DQ7/ CMD 2 DQ0–DQ15 ...

Page 26

V IH A0–A18/(A19) Note DQ0–DQ7/ CMD 2 DQ0–DQ15 ...

Page 27

TYP 1 PIN #1 INDEX .010 (0.25) .006 (0.15) 20 .007 (0.18) .005 (0.13) Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion ...

Page 28

TYP 1 PIN #1 INDEX .010 (0.25) .006 (0.15) 24 .007 (0.18) .005 (0.12) Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion ...

Page 29

TYP PIN #1 INDEX Notes: 1. Contact factory for availability 2. All dimensions in millimeters MAX/MIN or typical where noted. 3. Package width and length do not include mold protrusion; allowable mold protrusion is ...

Page 30

REVISION HISTORY Rev. 3, ...............................................................................................................................................................................8/02 • Removed PRELIMINARY designation t • Changed RS from 600ns (MIN) to 1,000ns (MIN) • Changed V from 0.45V (MAX) to 0.50V (MAX) OL Rev. 2, PRELIMINARY....................................................................................................................................................12/01 • Updated input capacitance specification t • Updated ...

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