MT48LC1M16A1TG-7S Micron Semiconductor Products, MT48LC1M16A1TG-7S Datasheet
MT48LC1M16A1TG-7S
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MT48LC1M16A1TG-7S Summary of contents
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... Plastic Package - OCPL* 50-pin TSOP (400 mil) • Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) 8ns (125 MHz) • Refresh with Self Refresh Mode at 64ms Part Number Example: MT48LC1M16A1TG-7S KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME CL = 3** -6 166 MHz 5.5ns ...
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GENERAL DESCRIPTION (continued) locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select ...
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TABLE OF CONTENTS Functional Block Diagram - 1 Meg x 16 ................. 3 Pin Descriptions ........................................................ 4 Functional Description ........................................ 5 Initialization ........................................................ 5 Register Definitions ............................................. 5 Mode Register ................................................ 5 Burst Length .............................................. 5 Burst Type ................................................. 5 ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# MODE REGISTER 12 REFRESH ADDRESS CONTROLLER A0-A10 REGISTER REFRESH 11 COUNTER 11 16Mb: x16 SDRAM 16MSDRAMx16.p65 – Rev. 8/99 FUNCTIONAL BLOCK DIAGRAM 1 Meg x 16 SDRAM ROW- MEMORY 11 ...
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PIN DESCRIPTIONS PIN NUMBERS SYMBOL 35 CLK 34 CKE 18 CS# 15, 16, 17 WE#, CAS#, RAS# 14, 36 DQML, DQMH 19 BA 21-24, 27-32, 20 A0-A10 DQ0- 11, 12, 39, 40, 42, DQ15 ...
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FUNCTIONAL DESCRIPTION In general, the SDRAM is a dual 512K x 16 DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x ...
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BA A10 Reserved Mode CAS Latency BT *Should program M11, M10 = ensure compatibility with future devices ...
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CAS Latency The CAS latency is the delay, in clock cycles, be- tween the registration of a READ command and the availability of the first piece of output data. The la- tency can be set ...
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COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Notes: 1) NAME (FUNCTION) COMMAND INHIBIT ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, re- gardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The ...
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AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank t until the precharge time ( RP) is completed. This is determined as ...
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OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the AC- TIVE command, which selects both the bank and ...
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READS READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are pro- vided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If ...
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CAS latency minus one. This is shown in Figure 7 for READ latencies of one, two and three; data element either the last of a burst of four ...
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CLK COMMAND ADDRESS DQ CAS Latency = 1 CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. 16Mb: x16 SDRAM 16MSDRAMx16.p65 – Rev. 8/ READ ...
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE burst may ...
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated) and a full-page burst may be truncated with a PRECHARGE command to the same bank. ...
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PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length ...
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WRITEs WRITE bursts are initiated with a WRITE com- mand, as shown in Figure 13. The starting column and bank addresses are pro- vided with the WRITE command and AUTO PRECHARGE is either enabled or disabled for that access. If ...
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Figure 16. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by ...
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Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is ...
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CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge on ...
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CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CON- CURRENT AUTO ...
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WRITE with AUTO PRECHARGE 3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data- out appearing CAS latency later. The PRECHARGE t to ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...
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TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L ...
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...
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TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row ...
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NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...
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ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ....................................... -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (ambient) .. ...
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CAPACITANCE PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11) (0°C ≤ T ≤ +70° CHARACTERISTICS PARAMETER Access time from CLK ...
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AC FUNCTIONAL CHARACTERISTICS (Notes 11) (0°C ≤ T PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data ...
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NOTES 1. All voltages referenced This parameter is sampled MHz 25° dependent on output loading and cycle rates. DD Specified values are obtained with minimum ...
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INITIALIZE AND LOAD MODE REGISTER CLK ( ( CKH t CKS ( ( ( ( ) ) ) ) CKE ( ( ( ( ) ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE 2 DQM ADDRESS BANK(S) High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks. power-down mode. TIMING ...
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CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH 3 DQM COLUMN m A0-A9 2 (A0 - A7) ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP 1 DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -6 -7 SYMBOL* MIN MAX ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP 1 DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -6 -7 SYMBOL* MIN MAX ...
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SINGLE READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE t AS ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 t AS ...
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ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS 3 DQM COLUMN m A0-A9 ROW ( ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...
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SINGLE WRITE – WITHOUT AUTO PRECHARGE T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 2 DQM A0-A9 ROW ROW A10 BANK DQ ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 3 DQM A0-A9 ROW ROW A10 BANK DQ t RCD ...
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TYP PIN # 1.00 (2X) NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side. ...