IS62WV5128BLL-55H Integrated Silicon Solution, IS62WV5128BLL-55H Datasheet

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IS62WV5128BLL-55H

Manufacturer Part Number
IS62WV5128BLL-55H
Description
Manufacturer
Integrated Silicon Solution
Datasheet

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IS62WV5128ALL
IS62WV5128BLL
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation
• TTL compatible interface levels
• Single power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
04/30/03
1.65V – 2.2V V
required
36 mW (typical) operating
2.5V – 3.6V V
9 µW (typical) CMOS standby
DD
DD
(IS62WV5128BLL)
(IS62WV5128ALL)
I/O0-I/O7
A0-A18
V
GND
DD
CS1
WE
OE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
1-800-379-4774
DESCRIPTION
The
speed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin
sTSOP (TYPE I), and 32-pin TSOP (Type II).
ISSI
MEMORY ARRAY
COLUMN I/O
IS62WV5128ALL / IS62WV5128BLL are high-
512K x 8
ISSI
's high-performance CMOS
ISSI
APRIL 2003
®
1

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IS62WV5128BLL-55H Summary of contents

Page 1

... Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV5128ALL and IS62WV5128BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin sTSOP (TYPE I), and 32-pin TSOP (Type II). ...

Page 2

... IS62WV5128ALL, IS62WV5128BLL PIN DESCRIPTIONS A0-A18 Address Inputs CS1 Chip Enable 1 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output NC No Connection V Power DD GND Ground PIN CONFIGURATION 32-pin TSOP (TYPE I), (Package Code T) 32-pin sTSOP (TYPE I) (Package Code H) A11 A13 A18 ...

Page 3

... Operating Range) Test Conditions -0.1 mA 1.65-2. 2.5-3. 0.1 mA 1.65-2. 2.1 mA 2.5-3.6V OL 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V GND GND Outputs Disabled OUT DD 1-800-379-4774 ISSI IS62WV5128BLL 2.5V - 3.6V 2.5V - 3.6V Unit +0 +0 °C W Min. Max. 1.4 — 2.2 — — 0.2 — 0.4 1 0 0.3 DD –0.2 0.4 –0.2 0.6 –1 1 –1 1 ® ...

Page 4

... V -0. REF See Figures 1 and 2 2.5V - 3.6V 3070 3150 1.5V 2.8V R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — ISSI Max. Unit IS62WV5128BLL (Unit) 0. -0.3V DD 5ns V REF See Figures 1 and 2 R1 VTM OUTPUT Including jig and scope 1-800-379-4774 ® Rev. A 04/30/03 ...

Page 5

... IS62WV5128ALL, IS62WV5128BLL POWER SUPPLY CHARACTERISTICS 62WV5128ALL (1.65V - 2.2V) Symbol Parameter I V Dynamic Operating CC DD Supply Current I Operating Supply 1 CC Current I TTL Standby Current 1 SB (TTL Inputs) I CMOS Standby 2 SB Current (CMOS Inputs) Note address and data inputs are cycling at the maximum frequency means no input lines change. ...

Page 6

... IS62WV5128ALL, IS62WV5128BLL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CS1 Access Time t ACS1 OE Access Time t DOE OE to High-Z Output t (2) HZOE OE to Low-Z Output t (2) LZOE CS1 to High-Z Output t HZCS1 ...

Page 7

... IS62WV5128ALL, IS62WV5128BLL AC WAVEFORMS (CS1, OE Controlled) READ CYCLE NO. 2 (1,3) ADDRESS OE CS1 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1 Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — Rev. A 04/30/ ...

Page 8

... IS62WV5128ALL, IS62WV5128BLL WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time WC CS1 to Write End t SCS1 t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA WE Pulse Width t PWE t Data Setup to Write End SD t Data Hold from Write End ...

Page 9

... IS62WV5128ALL, IS62WV5128BLL WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CS1 WE t DOUT DATA UNDEFINED DIN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE CS1 DOUT DATA UNDEFINED DIN Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 10

... IS62WV5128ALL, IS62WV5128BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR DATA RETENTION WAVEFORM (CS1 t SDR CS1 GND 10 Test Condition See Data Retention Waveform = 1.2V, CS1 V V – ...

Page 11

... IS62WV5128BLL-55H 70 IS62WV5128BLL-70T 70 IS62WV5128BLL-70T2 70 IS62WV5128BLL-70H Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 55 IS62WV5128BLL-55TI 55 IS62WV5128BLL-55T2I 55 IS62WV5128BLL-55HI 70 IS62WV5128BLL-70TI 70 IS62WV5128BLL-70HI Integrated Silicon Solution, Inc. — www.issi.com — Rev. A 04/30/03 Package TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I Package TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I ...

Page 12

... D 13.20 13.60 D1 11.70 11.90 E 7.90 8.10 e 0.50 BSC L 0.30 0.70 S 0.28 Typ. 0° 5° Integrated Silicon Solution, Inc. PK13197H32 Rev. B 04/21/ Inches Min Max Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protru- — 0.049 sions and should be measured from the bottom of the package ...

Page 13

... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

Page 14

... B 0.17 0.23 C 0.12 0.17 D 7.90 8.10 E 18.30 18.50 H 19.80 20.20 e 0.50 BSC L 0.40 0. Integrated Silicon Solution, Inc. PK13197T32 Rev. B 01/31/ SEATING PLANE Inches Min Max — 0.047 Notes: 1. Controlling dimension: millimeters, unless otherwise 0.002 0.010 0.007 0.009 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash ...

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