IS61LV5128-15TI Integrated Silicon Solution, IS61LV5128-15TI Datasheet
IS61LV5128-15TI
Related parts for IS61LV5128-15TI
IS61LV5128-15TI Summary of contents
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... CMOS input levels. The IS61LV5128 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV5128 is available in 36-pin 400-mil SOJ, 36- pin mini BGA, and 44-pin TSOP (Type II) packages. 512K X 8 DECODER ...
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... IS61LV5128 PIN CONFIGURATION 36 mini BGA I/ I/ GND E Vcc F I/O6 A18 A17 OE CE I/O7 A16 G A9 A10 A12 A11 H PIN DESCRIPTIONS A0-A18 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Vcc Power ...
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... IS61LV5128 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation T Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IS61LV5128 DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage ( Input Leakage LI I Output Leakage LO Note –3.0V for pulse width less than 10 ns. IL POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions = Max ...
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... IS61LV5128 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE CE to Low-Z Output t (2) LZCE CE to High-Z Output ...
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... IS61LV5128 AC WAVEFORMS (1,2) (Address Controlled) ( READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) (CE and OE Controlled) ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions. ...
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... IS61LV5128 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time Address Hold from HA t Address Setup Time SA WE Pulse Width t (4) 1 PWE WE Pulse Width (OE = LOW PWE t Data Setup to Write End SD t Data Hold from Write End ...
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... IS61LV5128 (1,2) (WE Controlled HIGH During Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE • ...
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... Plastic SOJ 12 IS61LV5128-12TI TSOP (Type II) 12 IS61LV5128-12BI mini BGA (8mmx10mm) 15 IS61LV5128-15KI 400-mil Plastic SOJ 15 IS61LV5128-15TI TSOP (Type II) 15 IS61LV5128-15BI mini BGA (8mmx10mm) ISSI Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www ...