IS80C32-40PL Integrated Silicon Solution, IS80C32-40PL Datasheet

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... MC004-1D 11/19/98 NOVEMBER 1998 GENERAL DESCRIPTION ISSI The IS80C52 and IS80C32 are high-performance microcontrollers fabricated using high-density CMOS technology. The CMOS IS80C52/32 is functionally compatible with the industry standard 8052/32 microcontrollers. The IS80C52/32 is designed with ROM (IS80C52 only); 256 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART ...

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... IS80C52 IS80C32 INDEX P1.5 7 P1.6 8 P1.7 9 RST 10 RxD/P3 TxD/P3.1 13 INT0/P3.2 14 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 Figure 2. IS80C52/32 Pin Configuration: 44-pin PLCC TOP VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA ...

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... IS80C52 IS80C32 P1.5 1 P1.6 2 P1.7 3 RST 4 RxD/P3 TxD/P3.1 7 INT0/P3.2 8 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 Figure 3. IS80C52/32 Pin Configuration: 44-pin PQFP Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/ P0.4/AD4 32 P0.5/AD5 P0.6/AD6 31 30 P0.7/AD7 ALE ...

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... IS80C52 IS80C32 V CC GND ADDRESS DECODER & 256 RAM ADDR BYTES RAM REGISTER B STACK POINT REGISTER PCON T2CON TL1 RCAP2L SBUF AND TIMER BLOCK PSEN TIMING ALE AND RST CONTROL EA OSCILLATOR XTAL1 XTAL2 4 P2.0-P2.7 P0.0-P0 DRIVERS DRIVERS P2 P0 LATCH LATCH ACC SCON ...

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... IS80C52 IS80C32 Table 1. Detailed Pin Description Symbol PDIP PLCC ALE P0.0-P0.7 39-32 43-36 P1.0-P1.7 1-8 2 P2.0-P2.7 21-28 24-31 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/98 PQFP I/O Name and Function 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In ...

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... IS80C52 IS80C32 Table 1. Detailed Pin Description (continued) Symbol PDIP PLCC P3.0-P3.7 10-17 11, 13- PSEN 29 32 RST 9 10 XTAL XTAL GND 20 22 Vcc PQFP I/O Name and Function 5, 7-13 I/O Port 3: Port 8-bit bidirectional I/O port with internal pullups ...

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... IS80C52 IS80C32 OPERATING DESCRIPTION The detail description of the IS80C52/32 included in this description are: •Memory Map and Registers •Timer/Counters •Serial Interface •Interrupt System •Other Information MEMORY MAP AND REGISTERS Memory The IS80C52/32 has separate address spaces for program and data memory. The program and data memory can 64K bytes long ...

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... IS80C52 IS80C32 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in Figure 6 shows that. Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect ...

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... IS80C52 IS80C32 SPECIAL FUNCTION REGISTERS (continued) Stack Pointer (SP) The Stack Pointer Register is eight bits wide incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H ...

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... IS80C52 IS80C32 Table 2: Special Function Register Symbol Description Direct Address ACC (1) Accumulator B (1) B register DPH Data pointer (DPTR) high DPL Data pointer (DPTR) low (1) IE Interrupt enable IP (1) Interrupt priority (1) P0 Port 0 (1) P1 Port 1 P2 (1) Port 2 P3 (1) Port 3 PCON Power control ...

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... IS80C52 IS80C32 The detail description of each bit is as follows: PSW: Program Status Word. Bit Addressable RS1 RS0 Register Description: CY PSW.7 Carry flag. AC PSW.6 Auxiliary carry flag. F0 PSW.5 Flag 0 available to the user for general purpose. RS1 PSW.4 Register bank selector bit 1. ...

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... IS80C52 IS80C32 IP: Interrupt Priority Register. Bit Addressable — — PT2 PS PT1 Register Description: — IP.7 Not implemented, reserve for future use — IP.6 Not implemented, reserve for future use PT2 IP.5 Defines Timer 2 interrupt priority level PS IP.4 Defines Serial Port interrupt priority level PT1 IP ...

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... IS80C52 IS80C32 TMOD: Timer/Counter Mode Control Register. Not Bit Addressable. Timer GATE GATE GATE When TRx (in TCON) is set and GATE=1, TIMER/ COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/ COUNTERx will run only while TRx=1 (software control) ...

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... IS80C52 IS80C32 T2CON: Timer/Counter 2 Control Register. Bit Addressable TF2 EXF2 RCLK TCLK EXEN2 TR2 Register Description: TF2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK = 1 or TCLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a ...

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... IS80C52 IS80C32 TIMER/COUNTERS The IS80C52/32 has three 16-bit Timer/Counter registers: Timer 0, Timer 1, and in addition Timer 2. All three can be configured to operate either as Timers or event Counters Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency ...

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... IS80C52 IS80C32 Mode 1: Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (TL1/TH1). As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to- 0000H overflow flag ...

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... IS80C52 IS80C32 Timer 2 Timer 16-bit Timer/Counter present only in the IS80C52/32. This is a powerful addition to the other two just discussed. Five extra special function registers are added to accommodate Timer 2 which are: the timer registers, TL2 and TH2, the timer control register, T2CON, and the capture registers, RCAP2L and RCAP2H ...

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... IS80C52 IS80C32 OSC DIVIDE 12 T2 PIN TRANSITION DETECTOR T2EX PIN NOTE: OSC FREQ. IS DIV BY 2, NOT 12 OSC DIVIDE PIN TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 Figure 14. Timer 2 in Baud Rate Generator Mode Note: 1. T2EX can be used as an additional external interrupt. ...

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... IS80C52 IS80C32 Timer Set-Up Tables 3 through 6 give TMOD values that can be used to set up Timers in different modes. It assumes that only one timer is used at a time. If Timers 0 and 1 must run simultaneously in any mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6) ...

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... IS80C52 IS80C32 Timer/Counter 2 Set-Up Except for the baud rate generator mode, the values given for T2C0N do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the Timer on. Table 7. Timer/Counter 2 Used as a Timer Mode Internal Control 16-Bit Auto-Reload ...

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... IS80C52 IS80C32 MULTIPROCESSOR COMMUNICATIONS Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, nine data bits are received, followed by a stop bit. The ninth bit goes into RB8; then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1 ...

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... IS80C52 IS80C32 Using Timer 2 to Generate Baud Rates In the IS80C52/32, setting TCLK and/or RCLK in T2CON selects Timer 2 as the baud rate generator. Under these conditions, the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 14 ...

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... IS80C52 IS80C32 More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/12 the oscillator frequency. Figure 15 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. ...

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... IS80C52 IS80C32 As data bits come in from the right, 1s shift to the left. When the start bit arrives at the leftmost position in the shift register, (which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated ...

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... IS80C52 IS80C32 WRITE TO SBUF S6 SERIAL PORT INTERRUPT REN ...

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... IS80C52 IS80C32 TIMER 1 TIMER 2 OVERFLOW OVERFLOW 2 SMOD SMOD = "0" "1" TCLK "1" "0" RCLK RXD TX CLOCK WRITE TO SBUF SEND S1P1 DATA SHIFT START BIT TXD TI RX CLOCK RXD BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT RI 26 IS80C52/32 INTERNAL BUS ...

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... IS80C52 IS80C32 PHASE 2 CLOCK (1/2 f OSC MODE 2 SMOD 1 2 SMOD 0 (SMOD IS PCON. 7) RXD TX CLOCK WRITE TO SBUF SEND S1P1 DATA SHIFT START BIT TXD TI STOP BIT GEN RX CLOCK RXD BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT RI Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/98 IS80C52/32 INTERNAL BUS ...

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... IS80C52 IS80C32 TIMER 1 TIMER 2 OVERFLOW OVERFLOW 2 SMOD SMOD = "0" "1" TCLK "0" "1" RCLK RXD TX CLOCK WRITE TO SBUF SEND S1P1 DATA SHIFT START TXD BIT TI STOP BIT GEN RX CLOCK RXD BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT ...

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... IS80C52 IS80C32 INTERRUPT SYSTEM The IS80C52/32 provides six interrupt sources: two external interrupts, three timer interrupts, and a serial port interrupt. These are shown in Figure 19. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON ...

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... IS80C52 IS80C32 Priority Level Structure Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IP (interrupt priority) at address 0B8H cleared after a system reset to place all interrupts at the lower priority level by default. A low- priority interrupt can be interrupted by a high-priority interrupt but not by another low-priority interrupt ...

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... IS80C52 IS80C32 Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it does not. It never clears the Serial Port or Timer 2 flags. This must be done in the user's software. The processor clears an external interrupt flag (IE0 or IE1) only if it was transition-activated ...

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... IS80C52 IS80C32 Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, ...

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... IS80C52 IS80C32 OTHER INFORMATION Reset The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running . The CPU responds by generating an internal reset, with the timing shown in Figure 21. ...

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... IS80C52 IS80C32 Power-on Reset An automatic reset can be obtained when V through capacitor and GND through an 8.2K resistor, providing the V rise time does not exceed CC 1 msec and the oscillator start-up time does not exceed 10 msec. This power-on reset circuit is shown in Figure 21. The CMOS devices do not require the 8.2K pulldown resistor, although its presence does no harm ...

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... IS80C52 IS80C32 Power-Saving Modes of Operation The IS80C52/32 has two power-reducing modes. Idle and Power-down. The input through which backup power is supplied during these operations is Vcc. Figure 23 shows the internal circuitry which implements these features. In the Idle mode (IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, and Timer blocks continue to be clocked, but the clock signal is gated off to the CPU ...

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... IS80C52 IS80C32 Table 12. Status of the External Pins During Idle and Power-down Modes. Mode Memory Idle Internal Idle External Power-down Internal Power-down External On-Chip Oscillators The on-chip oscillator circuitry of the IS80C52/ single stage linear inverter, intended for use as a crystal- controlled, positive reactance oscillator (Figure 24). In this ...

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... IS80C52 IS80C32 Note: When the frequency is higher than 24 MHz, please refer to Table 13 for recommended value of C1, C2, and R. Table 13. Recommended Value for C1, C2 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/98 XTAL2 R C1 Figure 26. For High Speed (> 24 MHz) Frequency Range 3 ...

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... IS80C52 IS80C32 ROM Verification The address of the program memory location to be read is applied to Port 1 and pins P2.4-P2.0. The other pins should be held at the “Verify” level are indicated in Figure 26. The contents of the addressed locations exits on Port 0. External pullups are required on Port 0 for this operation. ...

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... IS80C52 IS80C32 ROM Lock System The program lock system, when programmed, protects the ROM code against software piracy. The IS80C52/32 has a two-level program lock system (see Table 14) and a 32-byte encryption table. No matter what lock bit is, the user submits the encryption table with his or her code in verify ROM mode ...

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... IS80C52 IS80C32 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation T Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IS80C52 IS80C32 DC CHARACTERISTICS ( Vcc = 3.3V 10%; GND = 0V) A Symbol Parameter V Input low voltage (All except Input low voltage ( IL V Input high voltage IH (All except XTAL 1, RST Input high voltage (XTAL RST positive schmitt-trigger SCH threshold voltage V – ...

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... IS80C52 IS80C32 POWER SUPPLY CHARACTERISTICS Symbol Parameter Icc Power supply current Active mode Idle mode Power-down mode Note: 1. See Figures 28, 29, 30, and 31 for Icc test conditiions. Vcc RST Vcc P0 NC XTAL2 CLOCK XTAL1 SIGNAL EA GND Figure 28. Active Mode 42 Test conditions (1) Vcc = 5.0V ...

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... IS80C52 IS80C32 AC CHARACTERISTICS ( Vcc = 3.3V 10%; GND = 0V; Cl for Port 0, ALE and PSEN Outputs = 100 pF; Cl for other outputs = 80 pF) A Vcc — 0.5V 0.2Vcc — 0.1 0.45V Note: 1. Clock signal waveform for Icc tests in active and idle mode (t EXTERNAL MEMORY CHARACTERISTICS Symbol ...

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... IS80C52 IS80C32 EXTERNAL MEMORY CHARACTERISTICS (Continued) Symbol Parameter t Serial port clock cycle time XLXL t Output data setup to QVXH clock rising edge t Output data hold after XHQX clock rising edge t Input data hold after XHDX clock rising edge t Clock rising edge to XHDV ...

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... IS80C52 IS80C32 TIMING WAVEFORMS ALE t AVLL PSEN PORT 0 PORT 2 Figure 32. External Program Memory Read Cycle ALE PSEN RD t AVLL PORT 0 A7-A0 FROM RI OR DPL PORT 2 Figure 33. External Data Memory Read Cycle Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/98 t LHLL t t LLPL PLPH ...

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... IS80C52 IS80C32 ALE PSEN WR t AVLL PORT 0 A7-A0 FROM RI OR DPL PORT 2 Figure 34. External Data Memory Write Cycle 0 1 INSTRUCTION ALE CLOCK t QVXH 0 DATA OUT t XHDV DATA IN VALID Figure 35. Shift Register Mode Timing Waveform LLWL WLWH t QVWX t LLAX DATA OUT t AVWL ...

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... IS80C52 IS80C32 P1.0-P1.7 P2.0-P2.3 PORT 0 P2.7 Vcc – 0.5V 0.45V Vcc - 0.5V Note inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”. Timing measurements are made at V Integrated Silicon Solution, Inc. — 1-800-379-4774 MC004-1D 11/19/98 ADDRESS t AVQV DATA OUT ...

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