MSM82C51A-2JS Oki Semiconductor, MSM82C51A-2JS Datasheet
MSM82C51A-2JS
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MSM82C51A-2JS Summary of contents
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... Transmitting/receiving operations under double buffered configuration. • Error detection (parity, overrun and framing) • 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C51A-2RS) • 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C51A-2JS) • 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C51A-2GS-K) This version: Jan. 1998 MSM82C51A-2RS/GS/JS Previous version: Aug ...
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... Semiconductor FUNCTIONAL BLOCK DIAGRAM RESET CLK C DSR DTR CTS RTS Transmit Data Bus Buffer Buffer ( Transmit Read/Write Control Control Logic Recieve Modem Buffer Control ( Recieve Control MSM82C51A-2RS/GS/JS TXD TXRDY TXE TXC RXD RXRDY RXC SYNDET/BD 2/26 ...
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... TXD RXD GND TXC C RXRDY MSM82C51A-2RS/GS/ RXC 25 DTR 24 RTS 23 DSR 22 RESET 21 20 CLK 19 TXD TXEMPTY 18 CTS 17 SYNDET/BD 16 TXRDY ...
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... It is necessary to execute a function-setting sequence after resetting the MSM82C51A-2. Fig. 1 shows the function-setting sequence. If the function was set, the device is ready to receive a command, thus enabling the transfer of data by setting a necessary command, reading a status and reading/writing data. Internal Reset Fig. 1 Function-setting Sequence (Mode Instruction Sequence) ...
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... Command (setting of operation) 1) Mode Instruction Mode instruction is used for setting the function of the MSM82C51A-2. Mode instruction will be in “wait for write” at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a “mode instruction.” ...
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... Fig. 3 Bit Configuration of Mode Instruction (Synchronous PEN Charactor Length Parity Disable Synchronous Mode Number of Synchronous Charactors 2 Charactors MSM82C51A-2RS/GS/ bits 6 bits 7 bits 8 bits Odd Even Disable ...
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... Semiconductor 2) Command Command is used for setting the operation of the MSM82C51A- possible to write a command whenever necessary after writing a mode instruction and sync characters. Items to be set by command are as follows: • Transmit Enable/Disable • Receive Enable/Disable DTR, RTS • Output of data. ...
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... Semiconductor Status Word It is possible to see the internal status of MSM82C51A-2 by reading a status word. The bit configuration of status word is shown in Fig SYNDET DSR FE /BD Fig. 5 Bit Configuration of Status Word Standby Status It is possible to put the MSM82C51A-2 in “standby status” ...
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... If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed. CS (Input terminal) This is the “active low” input terminal which selects the MSM82C51A-2 at low level when the CPU accesses. The device won’ “standby status”; only setting CS = High. ...
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... RXD (input terminal) This is a terminal which receives serial data. RXRDY (Output terminal) This is a terminal which indicates that the MSM82C51A-2 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost ...
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... If a status word is read, the terminal will be reset. In “external synchronous mode, “this is an input terminal. A “High” on this input forces the MSM82C51A-2 to start receiving data characters. In “asynchronous mode,” this is an output terminal which generates “high level”output upon the detection of a “break” character if receiver data contains a “low-level” space between the stop bits of two continuous characters ...
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... OL "H" Output Voltage V OH Input Leak Current I LI Output Leak Current I LO Operating Supply I CCO Current Standby Supply I CCS Current Rating MSM82C51A-2RS MSM82C51A-2GS MSM82C51A-2JS –0 –0 +0.5 CC –0 +0.5 CC –55 to +150 0.9 0.7 Symbol Range – Symbol Min. ...
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... RD to Data Float Recovery Time between RD Address Stable before WR Address Hold Time for WR WR Pulse Width Data Set-up Time for WR Data Hold Time for WR Recovery Time between WR RESET Pulse Width MSM82C51A-2RS/GS/ 4 –40 to 85°C) CC Symbol Min. Max — ...
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... TXEMPTY RXDS t 17 RXDH 16¥, 64¥ Baud and for Synchronous Mode MSM82C51A-2RS/GS/ 4 –40 to 85°C) CC Unit Remarks Max. ns — Note 3 ns — — –50 — — — ...
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... Receiver Clock and Data (RXBAUD Counter starts here) RXD RXC (1 ¥ Mode) 8RXC Periods (16¥Mode) RXC (16 ¥ Mode) INT Sampling Pulse TPD t DTX Start bit t RPD t RPW 16 RXC Periods (16 ¥ Mode MSM82C51A-2RS/GS/ Data bit Data bit 3t CY 15/26 ...
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... Data Float Don't Care Data Stable Data Float MSM82C51A-2RS/GS/JS t TXRDY Clear Don't Care RXRDY Clear Data Float Data Out Active ...
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... CHAR2 CHAR1 SYNC CHAR2 CHAR3 CHAR4 PAR PAR PAR PAR PAR MSM82C51A-2RS/GS/JS Wr SBRK DATA CHAR 4 RxEn RxEn Err Res Wr Commond Wr Data SBRK CHAR5 Marking Spacing Marking Data SYNC State ...
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... Clock Length 2. Parity flag after a break signal is received (See Fig. 2.) When the MSM82C51A-2 is used in the asynchrous mode, a parity flag may be set when the next normal data is read after a break signal is received. A parity flag is set when the rising edge of the break signal (end of the break signal) is changed between the final data bit and the parity bit, through a RXRDY signal may not be outputted ...
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... Normal Operation RXD RXRDY The Start bit Is Shorter Than a 1/2 Data bit RXD ST RXRDY The Start bit Is a 1/2 Data bit (A problem of MSM82C51A-2) RXD ST RXRDY The Start bit Is Longer Than a 1/2 Data bit RXD ST RXRDY ST: Start bit SP: Stop bit P: Parity bit D ...
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... parity flag is set, but, no RXRDYsignal is outputted parity flag is set. and a RXRDY signal is outputted. MSM82C51A-2RS/GS/ ≠ ≠ D ...
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... High-speed device (New) M80C85AH M80C86A-10 M80C88A-10 M82C84A-2 M81C55-5 M82C37B-5 M82C51A-2 M82C53-2 M82C55A-2 Remarks Low-speed device (Old) M80C85A/M80C85A-2 8bit MPU 16bit MPU M80C86A/M80C86A-2 8bit MPU M80C88A/M80C88A-2 Clock generator M82C84A/M82C84A-5 RAM.I/O, timer M81C55 DMA controller M82C37A/M82C37A-5 USART M82C51A Timer M82C53-5 PPI M82C55A-5 MSM82C51A-2RS/GS/JS 21/26 ...
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... RD Rising to Data Difinition RD Rising to Data Float WR Pulse Width Data Setup Time for WR Rising Data Hold Time for WR Rising Master Clock Period Clock Low Time Clock High Time As shown above, the MSM82C51A-2 satisfies the characteristics of the MSM82C51A. Symbol MSM82C51A I +2 -400 mA ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C51A-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C51A-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C51A-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...
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... When the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less. Case 3: When an output of the other IC device is connected to the device. The MSM82C84A can be replaced by the MSM82C84A-2 when the I ASYNC pin of the MSM82C84A-2 has an allowance of 100 mA or more. MSM82C51A-2RS/GS/JS pin of the device to drive the OL 26/26 ...