CY39100V208-125NTC Cypress Semiconductor Corporation., CY39100V208-125NTC Datasheet
CY39100V208-125NTC
Specifications of CY39100V208-125NTC
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CY39100V208-125NTC Summary of contents
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Features • High density — 30K to 200K usable gates — 512 to 3072 macrocells — 136 to 428 maximum I/O pins — Twelve dedicated inputs including four clock pins, four global I/O control signal pins and four JTAG interface ...
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Delta39K Speed Bins Device V CC 39K30 3.3/2.5V 39K50 3.3/2.5V 39K100 3.3/2.5V 39K165 3.3/2.5V 39K200 3.3/2.5V Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs 208 EQFP 256 FBGA 28 × × 17 ...
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GCLK[3:0] GCTL[3:0] PLL and Clock MUX 4 4 GCLK[3: Channel PIM RAM Cluster Cluster RAM RAM GCLK[3: ...
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The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior ...
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Logic Block Logic Block Logic Block Logic Block Cluster Memory Figure 3. Delta39K Logic Block Cluster Diagram Logic Block The LB is the basic building block of the Delta39K architecture. It consists of a product term array, an intelligent product-term ...
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Macrocell Within each logic block there are 16 macrocells. Each macrocell accepts a sum product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial ...
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Embedded Memory Each member of the Delta39K family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each channel memory block is 4096 bits in size and ...
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The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs of the ...
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Dual-Port Array Configurable as Async/Sync Dual-Port or Sync FIFO Configurable and 512 x 8 block sizes Figure 6. Block Diagram of Channel Memory Block I/O Banks The Delta39K interfaces ...
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From Output PIM To Routing Channel I/O Signals There are four dedicated inputs (GCTL[3:0]) that are used as Global I/O Control Signals available to every I/O cell. These global I/O control signals may be used as output enables, register resets ...
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Programmable Bus Hold On each I/O pin, user-programmable-bus-hold is included. Bus-hold, which is an improved version of the popular internal pull-up resistor weak latch connected to the pin that does not degrade the device’s performance latch, ...
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Table 6 describes the valid phase shift options that can be used with or without an external feedback. Table example of the effect of all the available divide and phase shift options on a VCO output of ...
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CompactPCI Hot Swap The CompactPCI Hot Swap specification allows the removal and insertion of cards into CompactPCI sockets without switching-off the bus. Delta39K CPLDs can be used as a CompactPCI host or target on these cards. This feature is useful ...
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GCLK[3: PIM MCS Cluster Cluster RAM GCLK[3: PIM Cluster Cluster RAM GCLK[3: PIM ...
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Instruction Register TDI Bypass Reg. JTAG TMS TAP CONTROLLER Boundary Scan TCLK idcode Usercode ISR Prog. Data Registers Figure 11. JTAG Interface Configuration can begin in two ways. It can be initiated by toggling the Reconfig pin from LOW to ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature (39K200, 208 EQFP) ................................. – +125 C Storage Temperature (all other densities and packages) .............. – +150 C ...
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Capacitance Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK [9] C PCI-compliant PCI [10] DC Characteristics (I/ REF CCIO I/O Standards (V) ( LVTTL –2 mA N/A 3.3 –2 mA LVTTL –4 ...
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Switching Characteristics — Parameter Descriptions Parameter Combinatorial Mode Parameters Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the t PD horizontal or vertical channel associated with that ...
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Switching Characteristics — Parameter Descriptions Parameter t Delay from the clock pin to the input of the clock driver CKIN t Delay from the I/O pin to the input of the I/O register IOREGPIN PLL Parameters t Maximum cycle to ...
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Cluster Memory Timing Parameter Descriptions Parameter t Macrocell clock to cluster memory output clock in the same cluster MACCLMS2 Internal Parameters t Asynchronous cluster memory access time from input of cluster memory to output of cluster memory CLMCLAA Channel Memory ...
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Channel Memory Timing Parameter Descriptions Parameter Internal Parameters t Asynchronous channel memory access time from input of channel memory to output of channel memory CHMCHAA Switching Characteristics — Parameter Values 233 Parameter Min. Max. Combinatorial Mode Parameters t 7.2 PD ...
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Switching Characteristics — Parameter Values 233 Parameter Min. Max INDUTY [14] f 6.2 266 PLLO [14] f 12.5 133 PLLI f 100 266 PLLVCO P –0.3 +0.3 SAPLLI f 50 MPLLI JTAG Parameters t 25 JCKH t ...
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Fast Slew Rate I/O Standard t t IOD EA SSTL2 I –0.02 SSTL2 II –0.22 HSTL I 0.94 HSTL II 0.79 HSTL III 0.77 HSTL IV 0.44 Cluster Memory Timing Parameter Values 233 Parameter Min. Max. Asynchronous Mode Parameters t ...
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Channel Memory Timing Parameter Values Dual-Port Synchronous Mode Parameters t 9.5 CHMCYC1 t 5.0 CHMCYC2 t 3.0 CHMS t 0 CHMH t 10 CHMDV1 t 7.0 CHMDV2 t 8.5 CHMBDV t 8.5 CHMMACS1 t 4.8 CHMMACS2 t 4.6 MACCHMS1 t ...
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Switching Waveforms (continued) Registered Output with Synchronous Clocking (Macrocell) INPUT SYNCHRONOUS CLOCK REGISTERED OUTPUT Registered Input in I/O Cell DATA INPUT INPUT REGISTER CLOCK REGISTERED OUTPUT Clock to Clock INPUT REGISTER CLOCK MACROCELL REGISTER CLOCK PT Clock to PT Clock ...
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Switching Waveforms (continued) Asynchronous Reset/Preset RESET/PRESET INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable GLOBAL CONTROL INPUT OUTPUTS Document #: 38-03039 Rev. *H Delta39K™ ISR™ t PRW t PRO t PRR CPLD Family EA Page ...
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Switching Waveforms (continued) Cluster Memory Asynchronous Timing ADDRESS (AT THE CLUSTER INPUT) WRITE ENABLE INPUT t CLMCLAA OUTPUT Cluster Memory Asynchronous Timing 2 ADDRESS (AT THE I/O PIN) WRITE ENABLE INPUT t CLMAA OUTPUT Document #: 38-03039 Rev. *H READ ...
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Switching Waveforms (continued) Cluster Memory Synchronous Flow-Through Timing GLOBAL CLOCK t t CLMS CLMH ADDRESS WRITE ENABLE REGISTERED INPUT t CLMDV1 REGISTERED OUTPUT Cluster Memory Internal Clocking MACROCELL INPUT CLOCK CLUSTER MEMORY INPUT CLOCK CLUSTER MEMORY OUTPUT CLOCK Document #: ...
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Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS WRITE ENABLE INPUT GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS WRITE ENABLE INPUT GLOBAL CLOCK (INPUT REGISTER) GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED ...
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Switching Waveforms (continued) Channel Memory DP Asynchronous Timing ADDRESS A n-1 WRITE ENABLE DATA INPUT D OUTPUT n–1 Channel Memory Internal Clocking MACROCELL INPUT CLOCK CHANNEL MEMORY INPUT CLOCK CHANNEL MEMORY OUTPUT CLOCK Document #: 38-03039 Rev ...
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Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK FIFO READ CLOCK FIFO WRITE CLOCK FIFO READ OR WRITE CLOCK Channel Memory DP SRAM Flow-Through R/W Timing CLOCK t CHMS A ADDRESS n–1 WRITE ENABLE DATA D n–1 ...
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Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing CLOCK A ADDRESS n–1 WRITE ENABLE DATA D n–1 INPUT OUTPUT Dual-Port Asynchronous Address Match Busy Signal B ADDRESS ADDRESS B n–1 ADDRESS MATCH Document #: 38-03039 ...
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Switching Waveforms (continued) Dual-Port Synchronous Address Match Busy Signal CLOCK A ADDRESS A n–1 B ADDRESS B n–1 ADDRESS MATCH Document #: 38-03039 Rev CHMS t CHMBDV Delta39K™ ISR™ CPLD Family B n+1 t ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Empty/Write Timing PORT B CLOCK WRITE ENABLE REGISTERED INPUT EMPTY FLAG (Active LOW) PORT A CLOCK READ ENABLE RE REGISTERED OUTPUT Document #: 38-03039 Rev CHMCLK t t CHMFS CHMFH D ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK READ ENABLE REGISTERED OUTPUT FULL FLAG (Active LOW) PORT B CLOCK WRITE ENABLE REGISTERED INPUT Document #: 38-03039 Rev CHMCLK t t CHMFS CHMFH t CHMFRDV ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Programmable Flag Timing PORT B CLOCK WRITE ENABLE PROGRAMMABLE ALMOST EMPTY FLAG (active LOW) PORT A CLOCK READ ENABLE PORT B CLOCK WRITE ENABLE t CHMFO PROGRAMMABLE ALMOST FULL FLAG (Active LOW) PORT ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Master Reset Timing t CHMFRS MASTER RESET INPUT READ ENABLE / WRITE ENABLE t CHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS t CHMFRSF HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS t CHMFRSF REGISTERED OUTPUT C Y ...
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... CY39050V484-125MBC 39K50 125 CY39050V208-125NTI CY39050V256-125BBI 83 CY39050V208-83NTC CY39050V256-83BBC CY39050V388-83MGC CY39050V484-83MBC CY39050V208-83NTI CY39050V256-83BBI 39K100 200 CY39100V208B-200NTC CY39100V256B-200BBC CY39100V484B-200BBC CY39100V388B-200MGC CY39100V676B-200MBC Document #: 38-03039 Rev. *H Package Name Package Type NT208 208-Lead Enhanced Quad Flat Pack BB256 256-Lead Fine Pitch Ball Grid Array MB256 256-Lead Fine Pitch Ball Grid Array ...
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... Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K100 125 CY39100V208B-125NTC CY39100V256B-125BBC CY39100V484B-125BBC CY39100V388B-125MGC CY39100V676B-125MBC CY39100V208B-125NTI CY39100V256B-125BBI CY39100V484B-125BBI 83 CY39100V208B-83NTC CY39100V256B-83BBC CY39100V484B-83BBC CY39100V388B-83MGC CY39100V676B-83MBC CY39100V208B-83NTI CY39100V256B-83BBI CY39100V484B-83BBI 39K165 181 CY39165V208-181NTC CY39165V484-181BBC CY39165V388-181MGC CY39165V676-181MBC 125 CY39165V208-125NTC CY39165V484-125BBC CY39165V388-125MGC CY39165V676-125MBC CY39165V208-125NTI CY39165V484-125BBI 83 CY39165V208-83NTC CY39165V484-83BBC CY39165V388-83MGC CY39165V676-83MBC ...
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Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K200 181 CY39200V208-181NTC CY39200V484-181BBC CY39200V388-181MGC CY39200V676-181MBC 125 CY39200V208-125NTC CY39200V484-125BBC CY39200V388-125MGC CY39200V676-125MBC CY39200V208-125NTI CY39200V484-125BBI 83 CY39200V208-83NTC CY39200V484-83BBC CY39200V388-83MGC CY39200V676-83MBC CY39200V208-83NTI CY39200V484-83BBI [17] CPLD Boot EEPROM Part Numbers (Ordering Information) Speed Device ...
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Package Diagrams 208-Lead Enhanced Quad Flat Pack (EQFP) NT208 Document #: 38-03039 Rev. *H Delta39K™ ISR™ CPLD Family 51-85069-*B Page ...
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Package Diagrams (continued) Document #: 38-03039 Rev. *H 388-Lead Ball Grid Array MG388 Delta39K™ ISR™ CPLD Family 51-85103-*C Page ...
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Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE ...
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Package Diagrams (continued) TOP VIEW A1 CORNER ...
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Package Diagrams (continued) Pin Tables Table 8. Pin Definition Table Pin Name Function GCLK0-3 Input Global Clock signals 0 through 3 GCTL0-3 Input Global Control signals 0 through 3 GND Ground Ground IO/V Input/Output Dual function pin Reference ...
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Table 8. Pin Definition Table Pin Name Function Reconfig Input Pin to start configuration of Delta39K TCLK Input JTAG Test Clock TDI Input JTAG Test Data In TDO Output JTAG Test Data Out TMS Input JTAG Test Mode Select V ...
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Table 11. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 12 IO0 13 IO0 14 IO0 15 IO0 16 IO/V REF0 17 IO0 18 IO0 19 IO0 20 V CCIO0 [19] 21 IO0 [19] 22 IO0 GND ...
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Table 11. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 56 Reconfig 57 CCE 58 CCLK 59 V CCCNFG 60 MSEL 61 IO2 62 IO2 63 IO2 64 IO/V REF2 65 IO2 66 V CCIO2 67 GND 68 IO2 69 IO2 ...
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Table 11. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 100 GND 101 IO3 102 IO3 103 IO3 104 IO/V REF3 105 IO4 106 IO4 107 IO4 108 IO/V REF4 109 IO4 110 IO4 111 V CCIO4 112 GND 113 IO4 ...
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Table 11. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 144 IO5 145 IO5 146 IO5 147 IO5 148 V CCIO5 149 IO/V REF5 150 IO5 151 IO5 152 GND 153 GCLK1 154 GND 155 GCTL1 156 TDO 157 TCLK 158 ...
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Table 11. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 [19] 188 IO7 [19] 189 IO7 [19] 190 IO/V REF7 191 V CCIO7 192 IO7 193 IO7 194 IO7 195 IO7 196 IO/V REF7 197 IO7 198 IO7 199 V CCIO7 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 A19 NC A20 NC A21 IO6 A22 IO/V REF6 A23 IO6 A24 IO6 A25 IO6 A26 GND B1 IO7 IO7 B6 IO/V REF7 B7 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 C11 IO7 C12 IO7 [19] C13 IO7 [19] C14 IO6 C15 IO/V REF6 C16 IO6 C17 NC C18 IO6 C19 IO6 C20 IO6 C21 IO6 C22 NC C23 NC C24 IO6 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 E3 IO0 E4 GCTL0 E23 GCLK1 E24 IO5 E25 TDI E26 TDO IO0 F23 NC F24 IO5 F25 IO5 F26 IO5 G1 IO0 G2 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 K25 NC K26 NC L1 IO0 L2 IO0 L3 IO0 L4 IO0 L11 GND L12 GND L13 GND L14 GND L15 GND L16 GND L23 NC L24 IO/V REF5 L25 NC ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 P1 IO1 P2 IO/V REF1 [19] P3 IO1 [19] P4 IO1 P11 GND P12 GND P13 GND P14 GND P15 GND P16 GND P23 V CC [19] P24 IO5 [19] P25 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 CCPRG U23 V CCPRG U24 IO4 U25 IO4 U26 IO1 V4 V CCIO1 V23 V CCIO4 V24 NC V25 NC V26 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 AB25 IO4 AB26 IO4 AC1 Data AC2 Reconfig AC3 IO2 AC4 IO2 AC5 IO2 AC6 IO2 AC7 NC AC8 V CCIO2 AC9 V CCIO2 AC10 V CCCNFG AC11 IO2 AC12 V ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 AD17 IO3 AD18 IO/V REF3 AD19 IO3 AD20 IO3 AD21 IO3 AD22 IO3 AD23 IO3 AD24 NC AD25 IO/V REF3 AD26 IO3 AE1 CCE AE2 MSEL AE3 IO2 AE4 IO2 AE5 ...
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Table 12. 388 BGA Pin Table (continued) Pin CY39050 AF9 NC AF10 IO2 AF11 GND AF12 IO2 AF13 V CC [19] AF14 IO3 [19] AF15 IO3 AF16 IO3 AF17 IO3 AF18 IO3 AF19 IO3 AF20 IO3 AF21 NC AF22 NC ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 B8 IO B10 V CCPLL B11 V CCIO6 B12 IO6 B13 IO6 B14 IO6 B15 GND B16 TDO C1 IO0 C2 IO0 C3 GND C4 IO7 C5 IO7 C6 ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 E4 IO0 E5 IO7 E6 IO7 E7 IO7 [19] E8 IO7 [19] E9 IO6 E10 IO6 E11 IO6 E12 TMS E13 IO5 E14 IO5 E15 IO5 E16 IO5 F1 IO0 F2 ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 G16 IO5 [19] H1 IO0 [19] H2 IO0 [19] H3 IO0 H4 IO/V H5 IO0 H6 GCLK0 H7 GND H8 GND H9 GND H10 GND H11 GCLK1 H12 IO5 H13 IO/V ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 K12 IO4 K13 IO/V K14 V CCIO4 K15 V CCPRG K16 IO4 L1 IO1 CCIO1 L4 IO CCCNFG L6 Config_Done L7 IO2 [19] L8 IO2 ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 [19] N8 IO2 [19] N9 IO3 N10 IO/V N11 IO/V N12 IO3 N13 GND N14 IO4 N15 IO4 N16 IO/V P1 IO1 P2 IO1 P3 GND P4 CCE P5 IO2 P6 ...
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Table 13. 256 FBGA Pin Table (continued) Pin CY39030 T4 IO2 T5 IO2 T6 IO IO2 T9 IO2 T10 NC T11 IO/V T12 IO3 T13 IO3 T14 IO3 T15 IO3 T16 GND Table 14. 484 FBGA Pin ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 IO/V REF7 B9 NC B10 IO7 B11 IO7 B12 IO6 B13 IO6 B14 NC B15 IO/V REF6 B16 NC B17 IO6 B18 IO6 B19 V CCIO6 B20 NC ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 D7 IO7 D8 IO7 D9 IO/V REF7 D10 NC D11 IO6/Lock D12 IO6 D13 IO/V REF6 D14 IO/V REF6 D15 IO6 D16 NC D17 NC D18 IO6 D19 GND D20 NC ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 F7 IO7 F8 IO7 F9 V CCIO7 F10 V CCIO7 [19] F11 IO7 [19] F12 IO6 F13 V CCIO6 F14 V CCIO6 F15 IO6 F16 NC F17 GND F18 TDI F19 ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 IO7 H9 IO7 H10 IO7 [19] H11 IO7 [19] H12 IO6 H13 IO6 H14 IO6 H15 TMS H16 IO5 H17 IO5 H18 IO5 H19 IO5 H20 IO5 H21 ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 K7 IO/V REF0 GCTL0 K10 GND K11 GND K12 GND K13 GND K14 GCTL1 K15 NC K16 IO/V REF5 K17 V CCIO5 K18 NC K19 NC K20 NC ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 [19] M7 IO1 [19] M8 IO1 M9 IO1 M10 GND M11 GND M12 GND M13 GND M14 IO4 [19] M15 IO4 [19] M16 IO4 [19] M17 IO4 M18 NC M19 NC ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 CCCNFG P9 Config_Done P10 IO2 [19] P11 IO2 [19] P12 IO3 P13 IO3 P14 IO3 P15 NC P16 IO/V REF4 P17 V CCIO4 P18 V CC P19 ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 T7 GND T8 MSEL T9 IO/V REF2 T10 IO/V REF2 [19] T11 IO2 [19] T12 IO3 T13 IO/V REF3 T14 IO/V REF3 T15 IO3 T16 GND T17 IO4 T18 IO4 T19 ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 V7 IO2 CCCNFG V10 V CCIO2 V11 IO2 V12 IO2 V13 NC V14 V CCIO3 V15 IO3 V16 IO3 V17 IO3 V18 GND V19 NC V20 NC ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 Y7 IO2 Y10 IO/V REF2 Y11 IO2 Y12 IO3 Y13 IO/V REF3 Y14 IO3 Y15 IO3 Y16 IO3 Y17 IO3 Y18 NC Y19 NC Y20 NC Y21 ...
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Table 14. 484 FBGA Pin Table (continued) Pin CY39050 AB5 IO2 AB6 IO2 AB7 IO2 AB8 NC AB9 NC AB10 NC AB11 GND AB12 GND AB13 IO3 AB14 IO3 AB15 IO3 AB16 NC AB17 IO3 AB18 NC AB19 NC AB20 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 B22 NC NC B23 NC NC B24 NC NC B25 GND GND B26 GND GND C4 GND GND C5 NC IO/V ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 F6 GND GND F7 IO7 IO7 F8 IO7 IO7 F9 IO7 IO7 F10 IO7 IO7 F11 IO/V IO/V REF7 REF7 F12 IO/V IO/V REF7 REF7 F13 IO6/Lock IO6/Lock F14 IO6 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 J16 IO/V IO/V REF6 REF6 J17 IO6 IO6 J18 GND GND J19 TCLK TCLK J20 IO5 IO5 J21 IO5 IO5 J22 IO5 IO5 J23 IO5 IO5 J24 NC IO5 J25 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 M26 GND GND N2 GND GND N3 GND GND N4 IO0 IO0 N5 IO0 IO0 [19] N6 IO0 IO0 [19] N7 IO0 IO0 [19] N8 IO0 IO0 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 T10 V V CCCNFG CCCNFG T11 Config_Done Config_Done T12 IO2 IO2 [19] T13 IO2 IO2 [19] T14 IO3 IO3 T15 IO3 IO3 T16 IO3 IO3 T17 IO4 IO4 T18 IO/V ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 W20 IO4 IO4 W21 IO4 IO4 W22 IO4 IO4 W23 IO4 IO4 W24 NC IO4 W25 NC NC W26 IO1 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 AC4 GND GND AC5 NC IO2 AC6 V V CCIO2 CCIO2 AC7 IO/V IO/V REF2 REF2 AC8 IO2 IO2 AC9 IO2 IO2 AC10 IO2 IO2 AC11 NC V CCIO2 AC12 ...
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Table 15. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 AF13 GND GND AF14 GND GND AF15 NC NC AF16 NC V CCIO3 AF17 NC NC AF18 NC NC AF19 NC NC AF20 NC NC AF21 NC V CCIO3 AF22 ...
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Document History Page Document Title: Delta39K™ ISR™ CPLD Family CPLDs at FPGA Densities™ Document Number: 38-03039 Issue Orig. of REV. ECN NO. Date Change ** 106503 05/30/01 *A 107625 07/11/01 *B 109681 11/16/01 *C 112376 12/21/01 *D 112946 04/04/02 *E ...