MX97102QC Macronix International Co., MX97102QC Datasheet
MX97102QC
Available stocks
Related parts for MX97102QC
MX97102QC Summary of contents
Page 1
FEATURES • Pin-to-Pin and Register-to-Register compatible with Siemens 2186 • Full duplex 2B+D ISDN S/T Transceiver according to CCITT I.430 • GCI digital interface • 3 types of 8-bit CPU interface • Receive timing recovery with adaptively switched thresholds • ...
Page 2
BLOCK DIAGRAM S/T Interface Transmitter Multiframe control Receiver DPLL 7.68MHZ OSC FIGURE 2: FUNCTIONAL BLOCK DIAGRAM P/N:PM0473 Control and Data Interface signals PIDP0 PIDP1 Activation/ GCI B-channel Deactivation Interface Switching ECHO PDCL PFSC1 microprocessor interface 2 MX97102 LAP-D FIFO WATCH ...
Page 3
PIN DESCRIPTION (44-PIN) TABLE 1: MX97102 PIN DESCRIPTIONS LQFP PLCC PAD# PAD# PIN NAME I/O DESCRIPTION 37 41 PAD0(D0 PAD1(D1 PAD2(D2 PAD3(D3) I/O device PAD4(D4 PAD5(D5 PAD6(D6) 44 ...
Page 4
TABLE 1: MX97102 PIN DESCRIPTIONS(Continued) LQFP PLCC PAD# PAD# PIN NAME I PA0 51 6 PA1 50 5 PA2 64 18 PA3 63 17 PA4 55 10 PA5(EAW PBCL 52,53 7,8 PSDS1,2 6,57,61 11, 15 ...
Page 5
DC CHARACTERISTICS TABLE 3: DC CHARACTERISTICS Temperature from 0 to 70°C; VDD = 5V±5%, VSSA = 0V, VSSD = 0V Symbol Parameter VIL L-input voltage VIH H-input voltage VOL L-output voltage VOL1 L-output voltage (IDP0) IOL= 7mA VOH H-output voltage ...
Page 6
AC CHARACTERICS TABLE 4: CRYSTAL SPECIFICATION PARAMETER Frequency Frequency calibration tolerance Load capacitance Oscillator mode XTAL1 Clock Characteristics (external oscillator input) TABLE 5: CLOCK CHARACTERISTICS Parameter Limit values min. Duty cycle 1:2 TIMING WAVE FORM MICROPROCESSOR INTERFACE TIMING----INTERL BUS MODE ...
Page 7
ALE AD0-AD7 FIGURE 3(c) MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE A0-A5 FIGURE 3(d) NON-MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE MOTOROLA BUS MODE ALE CS ...
Page 8
R D0-D7 FIGURE 4(b) MICROPROCESSOR WRITE TIMING IN MOTOROLA BUS MODE AD0-AD5 FIGURE 4(c) NON-MULTIPLEXED ADDRESS TIMING IN MOTOROLA BUS MODE TABLE 6: PARAMETERS FOR MICROPROCESSOR INTERFACE TIMING PARAMETER ALE pulse witdh Address setup ...
Page 9
Functional and Operational Description ISDN ACCESS ARCHITECTURE MX97102 is designed especially for subscriber termi- nal equipment with S/T interfaces, Four wire, two pairs for transmission and receiption separately, are con- nected to the NT equipment at the user site. Via ...
Page 10
GCI CONNECTION With the GCI interface, MX97102 could connect differ- ent voice/data (V/D) application modules eight D-channel components may be connected to the D and C/I (Command/Indication) channels (TIC-bus). TIC-bus arbitration is also implemented in MX97102. Data transfers ...
Page 11
FSC1 CH0 IPD0 B1 B2 MONO (DD) IPD1 MONO D CIO B1 B2 (DU) SDS1 IDP0,1:768 kbit/s DCL :1536 kHz FSC1 :8 kHz The GCI interface is operated in the “open drain” mode in order to takes advantage of the ...
Page 12
If IDC is set to "0" (master mode): - IDP0 carries the MONITOR 1 and C/I 1 channels as output to peripheral (voice/data) devices; - IDP0 also carries the IC channels as output to other devices, if programmed (CxC1-0=01 in ...
Page 13
Microprocessor Access to B and IC Channels The microprocessor can access the B and IC channels at the GCI interface by reading the B1CR/B2CR or by reading and writing the C1R/C2R registers. Furthermore it is possible to loop back the ...
Page 14
S/T Interface Layer-1 Functions FSC IDP0 B1 B2 IC1 IC2 (DD) B1CR C2R B2CR C1R IDP1 B1 B2 IC1 IC2 (DU) Figure 6-3(a) SPCR : (CxC1, CxC0) = (0,0) Bx and ICx monitoring P/N:PM0473 Bx ICx BxCR CxR uP B1 ...
Page 15
S/T Interface Layer-1 Functions FSC IDP0 B1 B2 IC1 IC2 (DD) B1CR C2R B2CR C1R IDP1 B1 B2 IC1 IC2 (DU) Figure 6-3(b) SPCR : (CxC1, CxC0) = (0,0) Bx and ICx monitoring, ICx looping (SQXR : IDC = 0) ...
Page 16
S/T Interface Layer-1 Functions FSC IDP0 B1 B2 IC1 IC2 (DD) B1CR C1R C2R B2CR IDP1 B1 B2 IC1 IC2 (DU) Figure 6-3(c) SPCR : (CxC1, CxC0) = (1,0) Bx access from/to S/T transmission of constant value of S/T P/N:PM0473 ...
Page 17
S/T Interface Layer-1 Functions FSC IDP0 B1 B2 IC1 IC2 (DD) B1CR B2CR IDP1 B1 B2 IC1 IC2 (DU) Figure 6-3(c) SPCR : (CxC1, CxC0) = (1,1) Bx looping from/to S/T transmission of variable pattern of S/T P/N:PM0473 Bx Bx ...
Page 18
MONITOR channel handling The MONITOR channel protocol is a handshake proto- col used for high speed information exchange between the MX97102 and other devices. The usage of the MONITOR channel protocol (see Fig- ure 6-4 below): - For programming and ...
Page 19
The microprocessor may either enforce a "1" setting the control bit MRC1, MRC0 or MXC1, MXC0 of the MOCR register to logic 0, or enable the control of these bits internally by the MX97102 accord- ing ...
Page 20
As a maximum speed case (MAX=1): The transmitter can be designed for a higher data throughput than is provided by the general case described above. The transmitter can deactivate MX and transmit new data one frame time after MR is ...
Page 21
C/I-Channel Handling & TIC-Bus Access The command/indication channel carries real-time sta- tus information between the MX97102 and another de- vice connected to the GCI. - One C/I channel (called C/I 0) conveys the commands and indications between the layer-1 and ...
Page 22
S/T interface Line transceiver functions for the S/Y interface follow the electrical specifications of CCITT I.430. According to this standard, pseudo-ternary encoding with 100% pulse width is used on the S/T interface. For both receive and transmit direction, a 2:1 ...
Page 23
Activation/Deactivation An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT I.430. Fig- ure6-9 shows the state diagrams. Table7-2 and Table7-3 indicate the command and indication code descriptions. OUT IN IOM2 Ind. Cmd. State ...
Page 24
PU ARL Loop 3 closed ARL ARL ATI Loop 3 Act i0/ X Figure 6-9(b) State diagram : unconditional transitions Command (upstream) Abbr. Timing TIM Reset RS Send continuous zeros SCZ Send ...
Page 25
Note: When in the activated state (AI8/AI10) the 2B+D channels are only transferred from the GCI to the S/T interface if an “Activate Request” command is written to the CIX0 register. Indication Abbr. Power up PU Deactivate request DR Error ...
Page 26
D-channel Access The D-channel access procedure according to CCITT I.430 including priority management is fully implemented in the MX97102. By programmed the DIM2-0 (MODE register) to 001 or 011, stop/go bit is evaluated for D- channel access handling, that is, ...
Page 27
Frame Number NT-to-TE FA-Bit position NT-to-TE M Bit 1 ONE 2 ZERO 3 ZERO 4 ZERO 5 ZERO 6 ONE 7 ZERO 8 ZERO 9 ZERO 10 ZERO 11 ONE 12 ZERO 13 ZERO 14 ZERO 15 ZERO 16 ONE ...
Page 28
Test Functions The MX97102 provides several test and diagnostic func- tions which can be grouped ad follows: - digital loop via TLP (Test Loop, SPCR register) com- mand bit: IDP1 is internally connected with IDP0, out- put from layer 1 ...
Page 29
Only the logical connection identified through the ad- dress combination SAP1, TEI1 will be processed in the auto mode, all others are handled as in the non-auto mode. The logical connection handled in the auto-mode must have a window size ...
Page 30
Depending on the message transfer mode the address and control fields of received frames are processed and stored in the Receive FIFO or in special registers as depicted in Figure 6-11. Address Flag Auto-Mode SAP1,SAP2 FE, FC (U-and I-Frames) (Note ...
Page 31
When 32 bytes of a message longer than that are stored in the RFIFO, the CPU is prompted to read out the data by an RPF interrupt. The CPU must handle this interrupt before more than 32 additional bytes are ...
Page 32
HDLC Frame Flag Transmit I-Frame (XIF) Flag Auto Mode, 8-Bit Addr. Transmit I-Frame (XIF) Flag Auto Mode, 16-Bit Addr. Transmit Transparent Frame(XTF) Flag All Modes Symbol Descriptions :Generated automatically by MX97102 :Written initially by CPU (Info Register) :Loaded (repeatedly) by ...
Page 33
If a 2-byte address field has been selected, the MX97102 takes the contents of the XAD1 register to build the high byte of the address field, and the XAD2 register to build to low byte of the address field. Addi- ...
Page 34
Interrupt Structure and Logic Since the MX97102 provides only one interrupt request output (INT), the cause of an interrupt is determined by the microprocessor by reading the Interrupt Status Reg- ister (ISTA). In this register, seven interrupt sources can be ...
Page 35
A read of the ISTA register clears all bits expect EXI and CISQ. CISQ is cleared by reading CIR0. A read of EXIR clears the EXI bit in ISTA as well as the EXIR register. When all bits in ISTA ...
Page 36
MICROPROCESSOR INTERFACE CONNECTION Single-chip microcontroller, such as 8048, 8031 or 8051, can meet the need of MX97102. MX97102 is built in various microprocessor interface, it fits perfectly into almost any 8-bit microprocessor system environment. The microprocessor interface can be selected ...
Page 37
S/T INTERFACE Line transceiver functions for the S/T interface follows the electrical specifications of CCITTI.430. According to this standard, pseudo-ternary encoding with 100% pulse width is used on the S/T interface. For both re- +5V VDD 10uf VSSD VSSA GND ...
Page 38
INTERNAL REGISTER TABLE 8 : HDLC OPERATION AND STATUS REGISTERS Addr. Name R/W Bit7 Bit6 (hex) 00-1F FIFO R/W 20 ISTA R RME RPF 20 MASK W RME RPF 21 STAR R XDOV XFW 21 CMDR W RMC RRES RNR ...
Page 39
... IDC CFS 3C ADF3 R EMR EDR ADF4 R/W IMS 0 ORDERING INFORMATION PART NO. PACKAGE MX97102QC 44 PIN PLCC MX97102UC 64 PIN LQFP P/N:PM0473 Bit5 Bit4 Bit3 Bit2 Bit1 0 TLP C1C1 C1C0 C2C1 CODR0 CODR0 CODR0 CODR0 CIC0 CODX0 CODX0 CODX0 CODX0 1 ...
Page 40
REVISION HISTORY Rev. No. Description 1.1 Preliminary release 1.2 Change editing Add ordering information and revision history Change words in drawings Add "not used" pins in pin descriptions 1.3 Page6, Table 3 changed 1.4 Wording errors 1.5 Change feature description ...
Page 41
PACKAGE INFORMATION 44-PIN PLASTIC LEADED CHIP CARRIER (PLCC) ITEM MILLIMETERS INCHES A 17.53 ± .12 .699 ± .005 B 16.59 ± .12 .653 ± .12 C 16.59 ± .12 .653 ± .12 D 17.53 ± .12 .690 ± .12 E ...
Page 42
MX97102 42 ...