HY5PS121621CFP-C4 Hynix Semiconductor, HY5PS121621CFP-C4 Datasheet
HY5PS121621CFP-C4
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HY5PS121621CFP-C4 Summary of contents
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... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.8 / Oct. 2007 HY5PS12421C(L)FP HY5PS12821C(L)FP HY5PS121621C(L)FP HY5PS12421C(L)FP HY5PS12821C(L)FP HY5PS121621C(L)FP 1 ...
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Revision History Rev. 0.1 0.2 0.3 0.4 Updated IDD3P-S value/OCD Default Characteristics 0.5 Updated IDD spec for x8 org. on page 16 0.6 0.7 Updated Timing Patterns (DDR2-800 5/5/5 and 6/6/6) 0.8 Rev. 0.8 / Oct. 2007 History Preliminary IDD ...
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Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & ...
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Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface ...
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Pin Configuration & Address Table 128Mx4 DDR2 Pin Configuration(Top view: see balls through package) 1 VDD NC NC VSSQ VDDQ DQ1 NC VSSQ VDDL VREF CKE NC BA0 A10 VSS A3 A7 VDD A12 ROW AND COLUMN ADDRESS TABLE ...
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DDR2 PIN CONFIGURATION(Top view: see balls through package) 1 VDD NU, RDQS DQ6 VDDQ DQ4 VDDL NC VSS VDD ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size ...
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DDR2 PIN CONFIGURATION(Top view: see balls through package) 1 VDD DQ14 VSSQ VDDQ DQ12 VSSQ VDD DQ6 VSSQ VDDQ DQ4 VSSQ VDDL NC VSS VDD ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag ...
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PIN DESCRIPTION PIN TYPE Clock: CK and CK are differential clock inputs. All address and control input signals are CK, CK Input sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) ...
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PIN TYPE Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. For ...
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Maximum DC Ratings 2.1 Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any ...
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AC & DC Operating Conditons 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions (SSTL_1.8) Symbol Parameter VDD Supply Voltage VDDL Supply Voltage for DLL VDDQ Supply Voltage for Output VREF Input Reference Voltage VTT Termination Voltage 1. Min. ...
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DC & AC Logic Input Levels 3.2.1 Input DC Logic Level Symbol Parameter V (dc) dc input logic high IH V (dc) dc input logic low IL 3.2.2 Input AC Logic Level Symbol Parameter V (ac) ac input logic ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage IX 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, ...
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Output Buffer Characteristics 3.3.1 Output AC Test Conditions Symbol Parameter V Output Timing Measurement Reference Level OTR 1. The VDDQ of the device under test is referenced. 3.3.2 Output DC Current Drive Symbol I Output Minimum Source DC Current ...
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OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note 1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing,voltage, ...
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IDD Specifications & Test Conditions IDD Specifications(max) DDR2 800 Symbol x4/x8 IDD0 100 IDD1 100 IDD2P 8 IDD2Q 40 IDD2N IDD3P S 12 IDD3N 60 IDD4W 160 IDD4R 140 IDD5B 160 Normal 8 Power IDD6 Low ...
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IDD Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1-5) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = IDD0 t RAS min(IDD) ; ...
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Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA CL(IDD RCD(IDD)-1* t CK(IDD CK(IDD RC(IDD), t RRD = t RRD(IDD), IDD7 ...
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For purposes of IDD testing, the following parameters are to be utilized Speed Bin (CL-tRCD-tRP) CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RASmax(IDD) t RP(IDD) t RFC(IDD)-256Mb t RFC(IDD)-512Mb t RFC(IDD)-1Gb Detailed IDD7 ...
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Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, ...
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Timing Parameters by Speed Grade (Refer to notes for information related to this table at the following pages of this table) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width ...
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Parameter Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size ...
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & ...
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Parameter Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read ...
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General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For ...
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VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple- ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen- tial data strobe mode is ...
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Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used ...
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Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/ IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the ...
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Fig. a Illustration of nominal slew rate for tIS,tDS CK,DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V (dc)max IL V (ac)max IL Vss Delta TF V Setup Slew Rate REF = Falling Signal ...
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Fig. -b Illustration of tangent line for tIS,tDS CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V (dc)max IL V (ac)max IL Nomial line Vss Delta TF Tangent line[V Setup Slew Rate = ...
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Fig. -c Illustration of nominal line for tIH, tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min REF region V (dc) REF V (dc)max IL V (ac)max IL Vss Hold Slew Rate V ...
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Fig. -d Illustration of tangent line for tIH , tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF REF region V (dc)max IL V (ac)max IL Vss Tangent line[V Hold ...
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Derating Values for DDR2 400, DDR2 533 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 Command / 0.8 Address Slew 0.7 rate(V/ns) 0.6 0.5 0.4 0.3 0.25 0.2 0.15 ...
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For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating value listed in above Table. Setup(tIS) nominal slew rate for a rising signal is defined as the ...
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ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 18. tHZ and tLZ transitions occur ...
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DQS DQS 24. tWTR is at least two clocks (2*tCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the VIH(ac) level to the single-ended ...
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Package Dimensions Package Dimension(x4,x8) 60Ball Fine Pitch Ball Grid Array Outline A1 Ball Mar k A1 Ball Mark 1 0.80 Rev. 0.8 / Oct. 2007 10.50 +/- 0.10 <Top View> φ0.45 ± 0. ...
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Package Dimension(x16) 84Ball Fine Pitch Ball Grid Array Outline A1 Ball Mark A1 Ball Mark 1 2 0.80 Rev. 0.8 / Oct. 2007 10.50 +/- 0.10 <Top View> φ0.45 ± ...