LU6612 Agere Systems, LU6612 Datasheet
LU6612
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LU6612 Summary of contents
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... Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product. TM LU6612 FASTCAT for 10Base-T/100Base-TX General Autonegotiation ( IEEE 802.3u clause 28): — ...
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... Table 17. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions ................................................. 20 Table 18. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ........................................... 21 Table 19. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ............................................. 22 Table 20. Operation Modes of LU6612 ................................................................................................................. 23 Table 21. LU6612 Crystal Specifications ............................................................................................................... 23 Table 22 . Absolute Maximum Ratings .................................................................................................................. 24 Table 23 . Operating Conditions ............................................................................................................................ 24 Table 24 ...
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... Figure 6. MDIO Input Timing .................................................................................................................................. 25 Figure 7. MDIO Output Timing ............................................................................................................................... 25 Figure 8. MDIO During TA (Turnaround Read Transaction ........................................................................... 25 Figure 9. MII Timing Requirements for LU6612 ..................................................................................................... 27 Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ...................................................................... 28 Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK.......................................................... 28 Figure 12. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL ......................................................................... 29 Figure 13 ...
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... IEEE 802.3u 10Base-T specification, and over category 5, Type 1, UTP and Type 1 shielded twisted-pair cable, according to IEEE 802.3u 100Base-X specification. Figure 1 illustrates a functional overview of the LU6612 while Figure 2 details the functions. Figure 3 shows how the LU6612 interfaces to the twisted pair. MANAGEMENT ...
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... FASTCAT Single-FET for 10Base-T/100Base-TX 100 Mbits/s TRANSCEIVER FAR-END SCRAMBLER FAULT GEN SD RX STATE MACHINE COLLISION SD DETECT CAR_STAT CARRIER DETECT RXERR_ST ALIGNER DESCRAMBLER FAR-END 10 Mbits/s TRANSCEIVER LC100 LC10 LS10 MII AUTONEGOTIATION AND LINK MONITOR PMD PDT TX SD DCRU SD PDR PMD RX LS100 LU6612 TX/TY RX/RY 5-5136(F).cr1 5 ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Description (continued LU6612 1:1 220 220 75 0.01 F 0.001 1:1 0. 0.01 F 0.001 F Figure 3. Typical Twisted-Pair (TP) Interface Data Sheet July 2000 RJ- 0.01 F 5-5433.i.r3 Lucent Technologies Inc. ...
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... QS6612 Key Lucent’s LU6612 Quality Semiconductor Inc. QS6612. Figure 4. Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and Quality Semiconductor Inc. Parts Lucent Technologies Inc. FASTCAT Single-FET for 10Base-T/100Base-TX VDD 1.25 220 ...
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... ACTLED/PHYAD[ IOA 6 CC GNDIOA GNDT CLKREF 12 GNDBT TEST[0] 15 TEST[ LU6612 Figure 5. LU6612 Pinout Data Sheet July 2000 GNDDIGB 48 TX_CLK 47 RX_ER/RXD[4] 46 RX_DV 45 RX_CLK 44 COL 43 CRS 42 GNDIOC 41 RXD[0] 40 RXD[1] 39 RXD[2] 38 RXD[3] 37 GNDDIGA 36 V DIGA 35 CC ...
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... Receive Error. When high, RX_ER indicates the LU6612 has detected a coding error RXD[4] in the frame presently being transferred. RX_ER is synchronous with RX_CLK. When the encode/decode bypass (EDB) is selected through the MII management interface, this output serves as the RXD[4] output. This pin is only valid when LU6612 is in 100 Mbits/s mode. TX_CLK O 47 Transmit Clock ...
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... IO 25 Management Data Input/Output. This I/O is used to transfer control and status infor- mation between LU6612 and the station management. Control information is driven by the station management synchronous with MDC. Status information is driven by the LU6612 synchronous with MDC. Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4) ...
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... Analog ground for transmitter Analog +5 V power supply for equalizer and adaptation circuit Analog ground for adaptation circuit. Analog +5 V power supply for band-gap circuit Analog ground band-gap circuit Analog +5 V power supply for 10Base-T transmitter Analog ground for 10Base-T transmitter Description LU6612 11 ...
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... Clock Reference. Connect this pin RESET I 27 Full Chip Reset (Active-Low). Reset is an active-low signal. Reset must be asserted low for at least five LSCLK cycles. The LU6612 will come out of reset after 400 s. LSCLK1 must remain running during reset. BGREF[1:0] I 57:58 Band-Gap Reference. Connect these pins to a 24.9 k parasitic load capacitance should be less than 15 pF ...
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... MDIO during a read transaction. During a write to the LU6612, these bits are driven the station. During a read, the MDIO is not driven dur- ing the first bit time and is driven the LU6612 during the second bit time. ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX MII Station Management Register Overview The MII management 16-bit register (MR) set is implemented as described in Table 8 below. Table 8. MII Management Registers (MR) Register Symbol Address 0 MR0 Control Register 1 MR1 Status Register 2 MR2 PHY Identifier Register 1 3 MR3 PHY Identifier Register 2 ...
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... The default state This bit is set during powerup/ reset, when MODE[2:0] is 001 or 011. Collision Test. When this bit is set the LU6612 will assert the COL sig- nal in response to TX_EN. This bit should only be set when in loopback mode. ...
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... R Reserved. All bits will read 1.6 (NO_PA_OK) R Suppress Preamble. This bit is set indicating that the LU6612 accepts management frames with the preamble suppressed. (This function is not sup- ported by QS6611.) 1.5 (NWAYDONE) R Autonegotiation Complete. When this bit indicates the autonegotiation process has been completed ...
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... QS6611.) Acknowledge. This bit is written to a logic zero and ignored on read. Remote Fault. When set to 1, the LU6612 indicates to the link partner a remote fault condition. Pause. When set to 1, indicates that the LU6612 wishes to exchange flow control information with its link partner ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX MII Station Management Table 13. MR5—Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page) 1 Bit Type 5.15 (LP_NEXT_PAGE) R 5.14 (LP_ACK) R 5.13 (LP_REM_FAULT) R 5.12:10 R 5.9 (LP_100BASET4) R 5.8 (LP_100BASET_FD) R 5.7 (LP_100BASETX) R 5.6 (LP_10BASET_FD) R 5.5 (LP_10BASET) R 5.4:0 (LP_SELECT Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters ...
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... When this bit indicates the device will comply with the message. If the bit is a logic 0, the previous value of the transmitted link code word was a logic 1. If the bit the previous value of the transmitted link code word was a 0. Description LU6612 19 ...
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... LU6612 has detected and corrected a polarity reversal on the twisted pair. If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the LU6612. This bit is not valid in 100 Mbits/s operation. The default is 0. 28.5 (DISCON) R/LH Disconnect. If this bit indicates a disconnect. This bit will latch high until read ...
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... Packet Error Indication Enable. When this bit packet error code, which indicates that the scrambler is not locked, will be reported on RXD[3:0] of the LU6612 when RX_ER is asserted on the MII. When this bit will disable this function. The default is 0. 29.7 (RESERVED) R/W Reserved ...
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... REF10 is used for phase alignment. This bit defaults Serial Select. When this bit is set Mbits/s serial mode will be selected. When the LU6612 is in 100 Mbits/s mode, this bit will be ignored. The default Link Partner Mode. Setting this bit will allow 10 Mbits/s operation with link pulses disabled ...
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... July 2000 MODE Selection LU6612 can be forced to operate in specific operating modes. This is achieved by configuring the MODE pins to the appropriate values at powerup/reset. The strapping options of the MODE pins are latched on reset to set the default values of various registers. The values can be modified by writing into the registers. The MODE[2:0] pins have 100 k internal pull-ups ...
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... Operating Supply Voltage Power Dissipation: 100 Mbits Mbits/s Autonegotiating * Typical power dissipations are specified at 5.0 V and 25 °C. This is the power dissipated by the LU6612 transmitting over 100 meters of cable. Electrical Characteristics The following specifications apply for V Table 24. dc Characteristics Parameter TTL Inputs: ...
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... Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive conten- tion on MDIO during a read transaction. During a write to the LU6612, these bits are driven the station. During a read, the MDIO is not driven during the first bit time and is driven the LU6612 during the second bit time ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Timing Characteristics (Preliminary) Table 26. MII Data Timing (25 pF Load) Name t1 RXD[3:0], RX_ER, RX_DV, Valid to RX_CLK High t2 RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid t3 RX_CLK High t4 RX_CLK Low t5 RX_CLK Period t6 TX_CLK High t7 TX_CLK Low t8 TX_CLK Period t9 TXD[3:0], TX_EN, TX_ER, Setup to TX_CLK ...
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... Data Sheet July 2000 Timing Characteristics (Preliminary) RX_CLK RXD[3:0] RX_DV RX_ER TXD[3:0] Figure 9. MII Timing Requirements for LU6612 Lucent Technologies Inc. FASTCAT Single-FET for 10Base-T/100Base-TX (continued TX_CLK t7 TX_EN TX_ER t9 LSCLK TXD[3:0] TX_EN TX_ER t11 1st BIT OF J RX/RY COL ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Timing Characteristics (Preliminary) Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK Name t15 RX/RY Activity to CRS Assertion t16 RX/RY Activity to RX_CLK Valid t17 IDL to CRS Deassertion t18 Dead Signal to CRS Deassertion RX/RY CRS RX_CLK Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK Table 28 ...
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... Time to Assert COL; LU6612 Is Transmitting; Receive Activity Starts t25 Time to Deassert COL; LU6612 Is Transmitting; Receive Activity Ceases t26 Time to Assert COL; LU6612 Is Receiving; Transmit Activity Starts t27 Time to Deassert COL; LU6612 Is Receiving; Transmit Activity Ceases t28 COL Pulse Width (TRANSMITTING—RECEIVE COLLISION DETECTED) TX_EN RX/RY ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Timing Characteristics (Preliminary) Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) Name t29 RXD Setup Before RX_CLK Rising Edge t30 RXD Held Past RX_CLK Edge t31 RX_CLK Low to CRS Deassertion (at end of received packet) ...
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... COLLISION DETECTED) TX_EN RX/RY COL t24 Figure 14. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK Lucent Technologies Inc. FASTCAT Single-FET for 10Base-T/100Base-TX (continued) Parameter (RECEIVING—TRANSMIT COLLISON DETECTED) IDL t25 LU6612 Min Max Unit ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Timing Characteristics (Preliminary) Table 32. 100 Mbits/s MII Transmit Timing Name t40 Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion t41 Rising Edge of TX_CLK Following TX_EN Assertion to TX/TY t42 Rising Edge of TX_CLK Following TX_EN Deassertion to CRS Deassertion ...
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... CRS RX_CLK t44 RX_DV RX_ER RXD[3:0] Lucent Technologies Inc. FASTCAT Single-FET for 10Base-T/100Base-TX (continued) Parameter 1st BIT OF T Figure 16. 100 Mbits/s MII Receive Timing LU6612 Min Max — 170 — 210 — 210 — 210 t45 t46 5-3747(F).er1 ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Outline Diagram 64-Pin TQFP Dimensions are in millimeters. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.50 TYP 10.00 0.20 12.00 0. 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.05/0.15 Data Sheet July 2000 1.00 REF 0.25 GAGE PLANE SEATING PLANE 0.45/0.75 DETAIL A 0.106/0.200 0.19/0.27 0.08 M DETAIL B Lucent Technologies Inc. ...
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... Preliminary Data Sheet: Preliminary data sheets describe the characteristics of initial prototypes. Data Sheet: When a data sheet has the specifications of a product in full production and has complete parameter values considered final and is classified as a data sheet. Lucent Technologies Inc. FASTCAT Single-FET for 10Base-T/100Base-TX LU6612 35 ...
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... LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Ordering Information Device Code Comcode LU6612-T64-DB 108160680 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte ...