MX29LV640DBTI-90G Macronix International Co., MX29LV640DBTI-90G Datasheet
MX29LV640DBTI-90G
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MX29LV640DBTI-90G Summary of contents
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FEATURES GENERAL FEATURES • 8,388,608 4,194,304 x 16 switchable • Sector Structure - 8KB(4KW and 64KB(32KW) x 127 • Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable • Sector ...
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PACKAGE • 44-Pin SOP • 48-Pin TSOP • 48-Ball LFBGA • All Pb-free devices are RoHS Compliant PIN CONFIGURATION 44 SOP 44 A20 A21 2 43 A19 A18 A17 A10 A6 ...
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PIN DESCRIPTION SYMBOL PIN NAME A0~A21 Address Input Q0~Q14 Data Inputs/Outputs Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode) CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# Hardware Reset Pin, Active Low BYTE# Word/Byte Selection Input WP#/ACC Hardware ...
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BLOCK DIAGRAM CE# OE# CONTROL WE# INPUT RESET# LOGIC BYTE# WP#/ACC ADDRESS LATCH A0-AM AND BUFFER Q0-Q15/A-1 AM: MSB address P/N:PM1208 MX29LV640D T/B PROGRAM/ERASE HIGH VOLTAGE FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA ...
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Table 1. BLOCK STRUCTURE MX29LV640DT SECTOR GROUP ARCHITECTURE Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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MX29LV640DB SECTOR GROUP ARCHITECTURE Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords ...
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Table 2. BUS OPERATION--1 Mode Select RE- CE# SET# Device Reset L X Standby Mode Vcc± Vcc± 0.3V 0.3V Output H L Disable Read Mode H L Write(Note1 Accelerate H L Program Temporary Vhv X Sector-Group Unprotect Sector-Group ...
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BUS OPERATION--2 Item Control Input CE# WE# OE# Sector Lock Status L H Verification Read Silicon Manufacturer Code Read Silicon MX29LV640DT Read Silicon MX29LV640DB Read Indicator Bit L H (Q7) For ...
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WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih command cycle, all address are latched at the later falling edge of CE# and WE#, and ...
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RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready ...
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WRITE PROTECT (WP#) Another function of the WP#/ACC pin is to provide write protection function on the two outermost 8 Kbyte boot sectors. When ViL is asserted on WP#/ACC pin, the two boot sectors are protected regardless of the previous ...
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Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. Security silicon sector can also be protected by two methods. Note that ...
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POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected ...
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TABLE 3. MX29LV640D T/B COMMAND DEFINITIONS Read Reset Mode Mode Command Word 1st Bus Cyc Addr Addr XXX 555 Data Data F0 2nd Bus Cyc Addr 2AA Data 3rd Bus Cyc Addr 555 Data 4th Bus Cyc Addr X00 Data ...
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RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) ...
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AUTOMATIC PROGRAMMING The MX29LV640D T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user ...
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CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration ...
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RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. 3. When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle ...
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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV640D T/B features CFI mode. Host system can retrieve the operating characteristics, structure and vendor- specified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this ...
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Table 4-3. CFI Mode: Device Geometry Data Values Description Device size = number of bytes Flash device interface description (02=asynchronous x8/x16) Maximum number of bytes in buffer write = 2 Number of erase regions within device Index ...
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Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query - Primary extended table, unique ASCII string, PRI Major version number, ASCII Minor version number, ASCII Unlock recognizes address (0= recognize, 1= don't recognize) Erase suspend (2= to ...
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ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DC CHARACTERISTICS Symbol Description Iilk Input Leak Iilk9 A9 Leak Iolk Output Leak Icr1 Read Current(5MHz) Icr2 Read Current(1MHz) Icw Write Current Isb Standby Current Isbr Reset Current Isbs Sleep Mode Current Icp1 Accelerated Pgm Current, WP#/Acc pin(Word/Byte) Icp2 Accelerated ...
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SWITCHING TEST CIRCUITS Vcc TESTED DEVICE 0.1uF Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF Rise/Fall Times : 5ns In/Out reference levels :1.5V SWITCHING TEST WAVEFORMS 3.0V 0.0V INPUT P/N:PM1208 MX29LV640D T 1.5V ...
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AC CHARACTERISTICS Symbol Description Taa Valid data output after address Tce Valid data output after CE# low Toe Valid data output after OE# low Tdf Data output floating after OE# high (*Note 1) Toh Output hold time from the earliest ...
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Figure 1. COMMAND WRITE OPERATION CE# Vih Vil Tcs Vih WE# Vil Toes OE# Vih Vil Vih Addresses Vil Tas Vih Data Vil P/N:PM1208 MX29LV640D T/B Tcwc Tch Twph Twp VA Tah Tdh Tds DIN VA: Valid Address 32 REV. ...
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READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS Vih CE# Vil Vih WE# Vil Vih OE# Vil Vih Addresses Vil HIGH Z Voh Outputs Vol P/N:PM1208 MX29LV640D T/B Tce Toeh Toe Toh Taa Trc ADD Valid DATA Valid 33 Tdf HIGH ...
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AC CHARACTERISTICS Item Description Trp1 RESET# Pulse Width (During Automatic Algorithms) Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) Trh RESET# High Time Before Read Trb1 RY/BY# Recovery Time (to CE#, OE# go low) Trb2 RY/BY# Recovery Time (to WE# ...
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ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# WE# Tcs Tghwl OE# Last 2 Erase Command Cycle Twc 2AAh Address Data RY/BY# SA: 555h for chip erase P/N:PM1208 MX29LV640D T/B Tch Twp Twph Read Status Tah Tas SA ...
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Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1208 MX29LV640D T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...
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Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM CE# Tch Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc 2AAh Address Address 0 Tds Tdh 55h Data RY/BY# P/N:PM1208 MX29LV640D T/B Tbal Tas Sector Sector Sector Address 1 ...
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Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1208 MX29LV640D T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector ...
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Figure 8. ERASE SUSPEND/RESUME FLOWCHART P/N:PM1208 MX29LV640D T/B START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another ...
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Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# WE# Tcs Tghwl OE# Last 2 Program Command Cycle 555h Address Data RY/BY# Figure 10. Accelerated Program Timing Diagram (9.5V ~ 10.5V) Vhv WP#/ACC Vil or Vih 250ns P/N:PM1208 MX29LV640D T/B Tch Twhwh1 ...
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Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM WE# CE# Tghwl OE# 555h Address Data RY/BY# P/N:PM1208 MX29LV640D T/B Twhwh1 or Twhwh2 Tcep Tceph Tah Tas PA Tdh Tds A0h PD Tbusy Status DOUT REV. 1.6, AUG. 16, ...
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART next address P/N:PM1208 MX29LV640D T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm No Read Again ...
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SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 1us CE# WE# OE# Data 60h SA, A6 A1, A0 Vhv Vih RESET# P/N:PM1208 MX29LV640D T/B 150uS: Sector Protect 15mS: Chip Unprotect Verification 60h 40h VA VA ...
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Figure 14-1. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv Retry Count +1 Retry Count=25? Yes Device fail P/N:PM1208 MX29LV640D T/B START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait ...
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Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv Retry Count +1 Retry Count=1000? Device fail P/N:PM1208 MX29LV640D T/B START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes No All sectors protected? Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms ...
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Table 5. TEMPORARY SECTOR GROUP UNPROTECT Parameter Alt Description Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# Tvhhwl Trsp RESET# Vhv to WE# Low Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS CE# WE# RY/BY# Vhv ...
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Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Notes: 1. Temporary unprotect all protected sectors Vhv=9.5~10.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected. P/N:PM1208 MX29LV640D T/B Start Apply Reset# pin Vhv Volt Enter Program or ...
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Figure 17. SILICON ID READ TIMING WAVEFORM Vih CE# Vil Vih WE# Vil Vih OE# Vil Vhv Vih A9 Vil Vih A0 Vil Taa Vih A1 Vil Vih ADD Vil DATA Vih Q0-Q7 (Byte Mode) Vil DATA Vih Q0-Q15/A-1 (Word ...
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WRITE OPERATION STATUS Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Trc Address Taa Q7 Q0-Q6 Tbusy RY/BY# P/N:PM1208 MX29LV640D T/B Tdf VA Toh Complement Status Data True Status Data Status Data ...
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Figure 19. DATA# POLLING ALGORITHM Notes: 1. For programming, valid address meas program address. For erasing, valid address meas erase sectors address should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1208 MX29LV640D T/B Start ...
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Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Trc Address VA Taa Q6/Q2 Tbusy RY/BY Valid Address P/N:PM1208 MX29LV640D T/B Tdf VA Toh Valid Status Valid Status Valid Data (second ...
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Figure 21. TOGGLE BIT ALGORITHM Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1208 MX29LV640D T/B Start Read Q7-Q0 Twice ...
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AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE#) Parameter Description Telfl/Telfh CE# to BYTE# from L/H Tflqz BYTE# from L to Output Hiz Tfhqv BYTE# from H to Output Active Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Vcc(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Chip Erase Time Sector Erase Time Erase/Program Cycles Chip Programming Time Byte Mode Word Mode Accelerated Byte/Word Program Time Word Program Time Byte Programming Time Notes: 1. Typical program and erase times assume the following ...
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... MX29LV640DBMC-90G 90 MX29LV640DTTC-90G 90 MX29LV640DBTC-90G 90 MX29LV640DTXEC-90G 90 MX29LV640DBXEC-90G 90 MX29LV640DTXEI-90G 90 MX29LV640DBXEI-90G 90 MX29LV640DTTI-90G 90 MX29LV640DBTI-90G 90 * 44-pin SOP is only for Pachinko Socket P/N:PM1208 MX29LV640D T/B Ball Pitch/ PACKAGE Ball size 44 Pin SOP 44 Pin SOP 48 Pin TSOP(Normal Type) 48 Pin TSOP(Normal Type) 0.8mm/0.4mm 48 Ball LFBGA 0.8mm/0.4mm 48 Ball LFBGA 0.8mm/0.4mm 48 Ball LFBGA 0 ...
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PART NAME DESCRIPTION 640 P/N:PM1208 MX29LV640D T OPTION: G: Lead-free package SPEED: 90: 90ns TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M:SOP T: TSOP X: ...
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PACKAGE INFORMATION P/N:PM1208 MX29LV640D T/B 58 REV. 1.6, AUG. 16, 2008 ...
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P/N:PM1208 MX29LV640D T/B 59 REV. 1.6, AUG. 16, 2008 ...
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P/N:PM1208 MX29LV640D T/B 60 REV. 1.6, AUG. 16, 2008 ...
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REVISION HISTORY Revision No. Description 1.0 1. Modified Tvcs from 50us(Min.) to 100us(Min.) 2. Modified latch-up protected to 250mA-->100mA 3. Modified latch-up characteristics 4. Modified sector erase resume section ...should be a 400us-->4ms P24 5. Modified "sector erase time" from ...
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... Fax: +886-2-2509-2200 Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Singapore Office Macronix Pte. Ltd. 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 62 ...