180NQ045R ATMEL Corporation, 180NQ045R Datasheet

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180NQ045R

Manufacturer Part Number
180NQ045R
Description
45V 180A Schottky DISCR. (R) Diode in a D-67 HALF-Pak package
Manufacturer
ATMEL Corporation
Datasheet

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Introduction
The M67204E implement a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the TEMIC FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin resets the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Features
Rev. F – June 30, 1999
First-in first-out dual port memory
4096
Fast access time: 40, 50 ns
Wide temperature range : – 55 C to + 125 C
9 organisation
9 CMOS Parallel FIFO Rad Tolerant
Using an array of eigh transistors (8 T) memory cell, the
M67204E combine an extremely low standby supply
current (typ = 1.0 A) with a fast access time at 40 ns
over the full temperature range. All versions offer battery
backup data retention capability with a typical power
consumption at less than 2 W.
The M67204E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S), ESA
SCC 9000 and QML.
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation 2 V data retention
TTL compatible
Single 5 V
High performance SCMOS technology
10 % power supply
M67204E
1

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180NQ045R Summary of contents

Page 1

K 9 CMOS Parallel FIFO Rad Tolerant Introduction The M67204E implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and ...

Page 2

M67204E Interface Block Diagram Pin Configuration 2 DIL ceramic 28 pin 600 mils FP 28 pin 400 mils (Preview) (top view ...

Page 3

Pin Names NAMES DESCRIPTION I0–8 Inputs Q0–8 Outputs W Write Enable R Read Enable RS Reset EF Empty Flag Signal Description Data In (I0 - I8) Data inputs for 9-bit data Reset (RS) Reset occurs whenever the Reset (RS) input ...

Page 4

M67204E Read Enable (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided that the Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with standing ...

Page 5

Functional Description Operating Modes Single Device Mode A single M67204E may be used when the application requirements are for 4096 words or less. The M67204E is Figure 2. Block Diagram of Single 4K 9 FIFO. (HALF–FULL FLAG) WRITE DATA IN ...

Page 6

M67204E Table 1 : Reset and retransmit Single Device Configuration/Width Expansion Mode INPUTS MODE MODE RS RT Reset 0 X Retransmit 1 0 Read/Write 1 1 Note : 4. Pointer will increment if flag is high. Table 2 : Reset ...

Page 7

FIFO stack. The data is enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the first ...

Page 8

M67204E Figure 6. Bidirectional FIFO Mode SYSTEM Electrical Characteristics Absolute Maximum Ratings Supply voltage (VCC – GND ...

Page 9

DC Parameters Parameter P t Description Operating CCOP (8) supply current I Standby CCSB (9) supply current I Power down CCPD (10) current Notes : 8. Icc measurements are made with outputs open ...

Page 10

M67204E SYMBOL (16) SYMBOL (17) SYMBOL (16) SYMBOL (17) READ CYCLE TRLRL tRC Read cycle time TRLQV tA Access time TRHRL tRR Read recovery time TRLRH tRPW Read pulse width (19) TRLQX tRLZ Read low to data low Z (20) ...

Page 11

SYMBOL (16) SYMBOL (17) SYMBOL (16) SYMBOL (17) EXPANSION TWLXOL tXOL Read/Write to XO low TWHXOH tXOH Read/Write to XO high TXILXIH tXI XI pulse width TXIHXIL tXIR XI recovery time TXILRL tXIS XI set-up time Notes : 16. STD ...

Page 12

M67204E Figure 9. Full Flag from Last Write to First Read. Figure 10. Empty Flag from Last Read to First Write. Figure 11. Retransmit. Notes : 23. EF, FF and HF may change status during Retransmit, but flags will be ...

Page 13

Figure 12. Empty Flag Timing Figure 13. Full Flag Timing Figure 14. Half-Full Flag Timing. Rev. F – June 30, 1999 M67204E 13 ...

Page 14

M67204E Figure 15. Expansion Out. Figure 16. Expansion In. Figure 17. Read Data Flow – Through Mode. 14 Rev. F – June 30, 1999 ...

Page 15

Figure 18. Write Data Flow – Through Mode. Ordering Information TEMPERATURE RANGE PACKAGE version pin FP 400 mils CP = Side brazed 28 pins 300 mils 0 = Dice form M ...

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