HY29F040AT-70 Hynix Semiconductor, HY29F040AT-70 Datasheet

HY29F040AT-70

Manufacturer Part Number

HY29F040AT-70

Description

HY29F040AT-70512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory

Manufacturer

Hynix Semiconductor

Datasheet

1.HY29F040AC-90.pdf (40 pages)

Specifications of HY29F040AT-70

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Bonase Electronics (HK) Co., Limited

Part Number:

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KEY FEATURES

· · · · · 5.0 V ± 10% Read, Program, and Erase

· · · · · High performance

· · · · · Compatible with JEDEC-Standard Commands

· · · · · Minimum 100,000 Program/Erase Cycles

· · · · · Sector Erase Architecture

· · · · · Erase Suspend/Resume

DESCRIPTION

The HY29F040A is a 4 Megabit, 5.0 volt-only CMOS

Flash memory device organized as a 512K bytes

of 8 bits each. The device is offered in standard

32-pin PDIP, 32-pin PLCC and 32-pin TSOP pack-

ages. It is designed to be programmed and

erased in-system with a 5.0 volt power-supply and

can also be reprogrammed in standard PROM

programmers.

The HY29F040A offers access times of 55 ns, 70

ns, 90 ns, 120 ns and 150 ns. The device has sepa-

rate chip enable (/CE), write enable (/WE) and out-

put enable (/OE) controls. Hyundai Flash memory

devices reliably store memory data even after

100,000 program/erase cycles.

The HY29F040A is entirely pin and command set

compatible with the JEDEC standard for 4 Mega-

bit Flash memory devices. The commands are writ-

ten to the command register using standard micropro-

cessor write timings. Register contents serve as

input to an internal state-machine which controls

the erase and programming circuitry. Write cycles

also internally latch addresses and data needed

for the programming and erase operations.

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licences are implied.

Rev.03/Aug.97

Hyundai Semiconductor

- Minimizes system-level power requirements

- 55 ns access time

- Uses software commands, pinouts, and

- Eight equal size sectors of 64K bytes each

- Any combination of sectors can be erased

- Suspend a sector erase operation to allow a

packages following industry standards for

single power supply Flash memory

concurrently; also supports full chip erase

data read or programming in a sector not

being erased within the same device

512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory

· · · · · Internal Erase Algorithms

· · · · · Internal Programming Algorithms

· · · · · Low Power Consumption

· · · · · Sector Protection

The HY29F040A is programmed by executing the

program command sequence. This will start the

internal byte programming algorithm that

automatically times the program pulse width and

also verifies the proper cell margin. Erase is

accomplished by executing either sector erase or

chip erase command sequence. This will start the

internal erasing algorithm that automatically times

the erase pulse width and also verifies the proper

cell margin. No preprogramming is required prior to

execution of the internal erase algorithm. Sectors

of the HY29F040A Flash memory array are electri-

cally erased via Fowler-Nordheim tunneling. Bytes

are programmed one byte at a time using a hot

electron injection mechanism.

The HY29F040A features a sector erase architecture.

The device memory array is divided into 8 sectors of

64K bytes each. The sectors can be erased indi-

vidually or in groups without affecting the data in

other sectors. The multiple sector erase and full

chip erase capabilities add flexibility to altering the

data in the device. To protect data in the device

from accidental program and erase, the device

also has a sector protect function. This function

hardware write protects the selected sectors. The sector

- Automatically erases a sector, any combination

- Automatically programs and verifies data at a

- 40 mA maximum active read current

- 60 mA maximum program/erase current

- 5 mA maximum standby current

- Hardware method disables any combination

of sectors, or the entire chip

specified address.

of sectors from a program or erase operation

HY29F040A Series

Related parts for HY29F040AT-70

HY29F040AT-70 Summary of contents

Page 1

KEY FEATURES · · · · · 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements · · · · · High performance - 55 ns access time · · · · · Compatible with JEDEC-Standard ...

Page 2

PROM programmer. The HY29F040A needs a single 5.0 volt power- supply for read, program and erase operation. In- ternally generated and well regulated voltages are provided for program and ...

PIN DESCRIPTION Pin Name Pin Function A0 - A18 Address Inputs DQ0 - DQ7 Data Input/Output /CE Chip Enable /OE Output Enable /WE Write Enable Vss Device Ground Vcc Device Power Supply (5.0V ± for -70, -90, -120 ...

Page 4

BUS OPERATION Table 1. Bus Operations (1) OPERATION (2) Electronic ID Manufacturer Code (2) Electronic ID Device Code (3) Read Standby Output Disable Write Enable Sector Protect Verify Sector Protect Notes ...

Page 5

Table 3. Sector Addresses A18 SA0 0 SA1 0 SA2 0 SA3 0 SA4 1 SA5 1 SA6 1 SA7 1 Electronic ID Mode The Electronic ID mode allows the reading out of a binary code from the device and ...

Page 6

Output Disable Mode With the /OE input at a logic high level (V from the device is disabled. This will cause the output pins high impedance state shown in Table 1 that /CE = ...

Page 7

COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the Command register. Writing incorrect addresses and data values or writing them in the improper Table 4. Command Definitions Bus First Bus Command Write Write Cycle ...

Page 8

Read/Reset Command The read or reset operation is initiated by writing the Read/Reset command sequence in to the com- mand register. Microprocessor read cycles retrieve the data from the memory. The device remains enabled for reads until the command register ...

Page 9

Two more 'unlock' write cycles are then followed by the chip erase command. Upon executing the Chip Erase command sequence, the device’s internal state machine executes an internal erase algorithm. The system is not required to ...

Page 10

During Sector Erase operation, data bit DQ7 shows a logical “0”. This operation is known as /Data Polling. Sector Erase operation is complete when data on DQ7 is a logical “1” (see Write Opera- tion Status section) at which time ...

Page 11

WRITE OPERATION STATUS Table 5. Write Operation Status Flags Status Byte Programming Operation In Progress Chip or Sector Erase Operation Erase Suspend Erase Suspended Sector Mode Non-Erase Suspended Sector Exceeded Byte Programming Operation Time Limits Chip or Sector Erase Operation ...

Page 12

During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth /WE pulse in the four write pulse sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the ...

Page 13

DATA PROTECTION The HY29F040A is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up the device automatically resets the internal state ma- chine in the Read ...

Page 14

Increment Address Program Command Sequence (Address/Command) Figure 1. Internal Programming Algorithm 14 START Write Program Command Sequence (see below) /Data Polling Device NO Last Address ? YES Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data HY29F040A ...

Page 15

W rite E rase and Sequ ence /Data P olling or Toggle Bit S uccessfu lly leted E rase leted rase Com m and Sequ ence (A ...

Page 16

START Read Byte (DQ0-DQ7), Addr = VA DQ7 = Data NO DQ5 = 1 Read Byte (DQ0-DQ7), Addr = VA DQ7 = Data Notes: 1. DQ7 is rechecked even if DQ5 = logical “1” because DQ7 may change simultaneously with ...

Page 17

START Read Byte (DQ0-DQ7) DQ6 = Toggle ? NO DQ5 = 1 ? Read Byte (DQ0-DQ7) DQ6 = Toggle ? Fail Notes: 1. DQ6 is rechecked even if DQ5 = logical “1” because DQ6 may stop toggling at the same ...

Page 18

ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Package .............................. -65° 125°C Ambient Temperature With Power Applied .......................... -55° 125°C Voltage with Respect to Ground All pins except A9 (1) .......................... -2. 7.0V Vcc ............................................... -2.0V ...

Page 19

V -0 2.0 V Figure 5. Maximum Negative Overshoot Waveform 2.0 V Figure 6. Maximum Positive Overshoot Waveform ...

Page 20

DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO (1) I Vcc Active Current CC1 (2,3) I Vcc Active Current CC2 I Vcc Standby Current ...

Page 21

DC CHARACTERISTICS (continued) CMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO I Vcc Active Current (1) CC1 (2,3) I Vcc Active Current CC2 I Vcc Standby ...

Page 22

AC CHARACTERISTICS Read Only Operations Parameter Symbol Description JEDEC Standard t t Read Cycle Time AVAV Address to AVQV ACC Output Delay t t Chip Enable to ELQV CE Output Delay t t Output Enable to GLQV ...

Page 23

Notes: 1. For -55 30pF including jig capacitance. 2. For all others 100pF including jig capacitance. Figure 7. Test Condition 5.0 V 2.7 ...

Page 24

AC CHARACTERISTICS Programming/Erase Operations Parameter Symbols JEDEC Standard Description t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...

Page 25

SWITCHING WAVEFORMS WAVEFORM Addresses OEH WE High Z Outputs Figure 8. AC Waveforms for Read Operations INPUTS OUTPUTS Must Be Steady Will Be Steady May Change Will Be Changing from from ...

Page 26

SWITCHING WAVEFORMS 5555H Addresses Data 5. GND Notes address of the memory location to be programmed data to be programmed at byte address. 3. /DQ7 is the output of ...

Page 27

SWITCHING WAVEFORMS t AS Addresses 5555H CE t GHWL WPH Data AAH VCS 5. GND Notes the sector address for Sector Erase. Address ...

Page 28

SWITCHING WAVEFORMS Notes: 1. DQ7 = ...

Page 29

SWITCHING WAVEFORMS Data Data (D Q0-D Q7) 5. Notes: 1. DQ6 stops toggling (The device has completed the internal program or erase operation) Figure ...

Page 30

Im p lem vic ile d Figure 13. Sector Protection Algorithm ...

Page 31

SWITCHING WAVEFORMS A18 A17 A16 12V A9 t VLHT 12V OE t VLHT Data 5. GND Notes Sector Address for initial sector Sector Address for next ...

Page 32

Increment Sector Address Notes: 1. SA0 = Sector Address for initial sector 2. SA7 = Sector Address for the last sector Figure 15. Sector Unprotect Algorithm 32 Start Protect All Sectors PLSCNT = 1 Set Up Sector Unprotect Mode A6 ...

Page 33

SWITCHING WAVEFORMS A6 A12 A16 12V A9 12V CE t 12V A18 A17 A0 A1 Data V CC 5.0V Notes: 1. Starts with SA0 and sequences to SA7. 2. See Figure 15 for details. Figure 16. AC ...

Page 34

AC CHARACTERISTICS Write / Erase / Program Operations Alternate /CE Controlled Writes Parameter Symbols JEDEC Standard Description t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX ...

Page 35

SWITCHING WAVEFORMS 5555H Addresses Data V CC Notes address of the memory location to be programmed data to be programmed at byte address. 3. DQ7 is the ...

Page 36

ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles LATCH UP CHARACTERISTICS Parameter Input Voltage with respect to Vss on all I/O pins Vcc Current Notes: 1. Includes all pins ...

Page 37

DATA RETENTION Parameter Minimum Pattern Data Retention Time Test Conditions Minimum 150 125 HY29F040A Unit Years Years 37 ...

Page 38

PACKAGE DRAWINGS - Physical Dimensions TSOP32 32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I. 1.20 MAX 0.25MM (0.0098") BSC PDIP32 32-Pin Plastic DIP (measured in inches) 1.640 1.680 32 32 Pin 1 I.D. .045 ...

Page 39

PACKAGE DRAWINGS - Physical Dimensions PLCC32 32-Pin Plastic Leaded Chip Carrier (measured in inches) .485 .495 .447 .453 . Pin 1 I.D .585 .547 .595 .553 .026 .050 REF. .032 TOP VIEW .009 .015 .125 .080 .140 .095 SEATING .400 ...

Page 40

ORDERING INFORMATION Hyundai products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: HY29F040A X – X VALID COMBINATIONS P-55, C-55, T-55, R-55 55ns P-55I, C-55I, T-55I, R-55I ...

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