SAA7146AHZ Philips Semiconductors, SAA7146AHZ Datasheet
SAA7146AHZ
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DATA SHEET SAA7146A Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1998 Apr 09 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) CONTENTS 1 FEATURES 1.1 Video processing 1.2 Audio processing 1.3 Scaling 1.4 Interfacing 1.5 General 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 General 7.2 PCI interface 7.3 Main control 7.4 Register Programming Sequencer (RPS) 7 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1 FEATURES 1.1 Video processing Full size, full speed video delivery to and from the frame buffer or virtual system memory enables various processing possibilities for any external PCI device Full bandwidth PCI-bus master write and read (up to ...
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... ORDERING INFORMATION TYPE NUMBER NAME SAA7146AH QFP160 SAA7146AHZ SQFP208 1998 Apr 09 2 The SAA7146A, Multimedia PCI-bridge highly integrated circuit for DeskTop Video (DTV) applications. The device provides a number of interface ports that enable a wide variety of video and audio ICs to be connected to the PCI-bus thus supporting a number of video applications ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 5 BLOCK DIAGRAM ok, full pagewidth 1998 Apr 09 5 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 6 PINNING Pin description for QFP160 SYMBOL PIN STATUS D1_A0 1 I/O D1_A1 2 I/O D1_A2 3 I/O D1_A3 4 I DDD1 SSD1 D1_A4 7 I/O D1_A5 8 I/O D1_A6 9 I/O D1_A7 10 I/O VS_A 11 I/O HS_A 12 I/O LLC_A 13 I/O PXQ_A 14 I DDD2 SSD2 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS AD PCI26 38 I/O AD PCI25 39 I/O AD PCI24 40 I/O C/BE# [3] 41 I/O IDSEL PCI23 43 I/O AD PCI22 44 I/O AD PCI21 45 I/O AD PCI20 46 I DDD6 SSD6 AD PCI19 49 I/O AD PCI18 50 I/O AD PCI17 51 I/O AD PCI16 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS AD PCI7 79 I/O AD PCI6 80 I SSD11 AD PCI5 82 I/O AD PCI4 83 I/O AD PCI3 84 I/O AD PCI2 85 I DDD11 SSD12 AD PCI1 88 I/O AD PCI0 89 I DDD12 SSD13 AD15 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS AD6 119 I/O AD7 120 I/O WS0 121 I/O SD0 122 I/O BCLK1 123 I/O WS1 124 O SD1 125 I/O WS2 126 O SD2 127 I/O V 128 P DDD17 V 129 P SSD18 WS3 130 O SD3 131 I/O BCLK2 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS HS_B 159 I/O PXQ_B 160 I/O Notes 1. For continuous CCIR 656 format at the D1_A port this pin must be set HIGH. 2. For continuous CCIR 656 format at the D1_B port this pin must be set HIGH. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Pin description for SQFP208 SYMBOL PIN STATUS SSD0 D1_A0 2 I/O D1_A1 3 I/O D1_A2 4 I/O D1_A3 5 I DDD1 n. SSD1 D1_A4 9 I/O D1_A5 10 I/O D1_A6 11 I/O D1_A7 12 I DDD2 n. SSD2 VS_A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS SSD5 AD PCI31 40 I/O AD PCI30 41 I/O AD PCI29 42 I/O AD PCI28 43 I DDD6 n. SSD6 AD PCI27 47 I/O AD PCI26 48 I/O AD PCI25 49 I/O AD PCI24 50 I DDD7 n. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS STOP# 79 I/O PERR n.c. 81 PAR 82 I/O C/BE# [ DDD10 n. SSD11 AD PCI15 87 I/O AD PCI14 88 I/O AD PCI13 89 I/O AD PCI12 90 I DDD11 n. SSD12 AD PCI11 94 I/O AD PCI10 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS AD15 120 I/O AD14 121 I/O AD13 122 I/O AD12 123 I/O V 124 P DDD15 n.c. 125 V 126 P SSD17 AD11 127 I/O AD10 128 I/O AD9 129 I/O AD8 130 I/O V 131 P DDD16 n.c. 132 V 133 P SSD18 RWN_SBHE ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PIN STATUS BCLK1 161 I/O WS1 162 O SD1 163 I/O WS2 164 O SD2 165 I/O V 166 P DDD20 n.c. 167 V 168 P SSD22 WS3 169 O SD3 170 I/O BCLK2 171 I/O WS4 172 I/O SD4 173 I/O ACLK 174 ...
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... B; note 2 reserved pin; do not connect digital supply voltage 25 (3.3 V) reserved pin; not connected internally reserved pin; do not connect 1 SAA7146AHZ 52 Fig.3 Pin configuration SAA7146AHZ (SQFP208). 16 Product specification SAA7146A DESCRIPTION 156 105 MHB046 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7 FUNCTIONAL DESCRIPTION This chapter provides information about the features realized with this device. First, a general, thus short, description of the functionality is given. The following sections deal with the single features in a detailed manner. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2 PCI interface This section describes the interface of the SAA7146A to the PCI-bus. This includes the PCI modules, the DMA controls of the video, audio and data channels, the Memory Management Unit (MMU) and the Internal Arbitration Control (INTAC) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) andbook, full pagewidth 1998 Apr 09 19 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 1 Configuration space registers ADDRESS NAME (HEX) 00 Device ID Vendor ID 04 Status Register Command Register 08 Class Code Revision ID 0C Latency 10 Base Address Register 2C Subsystem ID Subsystem vendor ID 3C Max_Lat Min_Gnt Interrupt Pin ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2.2 V DMA IDEO CONTROL The SAA7146A’s DMA control is able to support up to three independent video targets or sources respectively. For this purpose it provides three video DMA channels. Each channel consists of a FIFO, a FIFO Input Control (FINC) placed on the video side of the FIFO, and a FIFO Control (FICO) placed on the PCI side of the FIFO ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 3 Video DMA control registers OFFSET NAME BIT (HEX) 00 BaseOdd1 BaseEven1 ProtAddr1 and 0 0C Pitch1 Page1 ME1 Limit1 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 28 RW2 2 Swap2 1 and 0 2C NumLines2 NumBytes2 BaseOdd3 BaseEven3 ProtAddr3 and 0 3C Pitch3 Page3 ME3 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) The video channels provide 32 bits of data signals and 4 bits of Byte Enable (BE) signals, End-Of-Line (EOL), End-Of-Window (EOW), Begin-Of-Field (BOF), Line-Locked Clock (LLC), Odd/Even signal (OE) and a Valid Data (VD) signal. To start a video data transfer, e.g. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 4 Protection violation handling modes LIMIT PV 0000 0 Lock input of FIFO and empty FIFO (only in write mode). Unlock FIFO and start next transfer using the base address at the detection of BOF. 0000 0 Restart immediately at base address ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2.3 A DMA UDIO CONTROL The SAA7146A provides up to four audio DMA channels, each using a FIFO of 24 Dwords. Two channels are read only (A1_in and A2_in) and two channels are write only (A1_out and A2_out) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME (HEX) AC BaseA2_in ProtA2_in and 0 B4 PageA2_in MEA2_in LimitA2_in PVA2_in BaseA2_out ProtA2_out and 0 C0 PageA2_out ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2 EMORY ANAGEMENT 7.2.4.1 Introduction To perform DMA transfers, physically continuous memory space is needed. However, operating systems such as Microsoft Windows are working with virtual demand paging, using a MMU to translate linear to physical addresses. Memory allocation is performed in the linear address space, resulting in fragmented memory in the physical address space ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Physical memory handbook, full pagewidth (4 kbyte pages) 00000H 00007H 0000FH 00017 H 0001FH = allocated memory space = page table 1998 Apr 09 PAGE TABLE BASE ADDRESS (00006H) Page table 000H 00001000H 00008000H 00009000H ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2.5 I NTERNAL ARBITRATION CONTROL The SAA7146A has up to three video DMA channels, four audio DMA channels and three other DMA channels (RPS, MMU and DEBI) each trying to get access to the PCI-bus. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 6 Arbitration control registers OFFSET NAME (HEX) 48 BurstDebi Burst3 Thresh3 Burst2 Thresh2 Burst1 Thresh1 4C BurstA1_in ThreshA1_in BurstA1_out ThreshA1_out 17 and 16 BurstA2_in ThreshA2_in BurstA2_out ThreshA2_out Table 7 Burst length definition VALUE 000 1 Dword ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.2.6 S TATUS INFORMATION OF THE Table 9 lists the status information that the PCI interface makes available to the user in addition to the interrupt sources that are described later. This information is read only. Table 9 Status bits of the DMA control ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 10 Main control register 1 OFFSET NAME BIT (HEX) Mask word FC M15 to M00 Control word FC MRST_N ERPS1 ERPS0 EDP EVP EAP EI2C TR_E_DEBI TR_E_1 TR_E_2 TR_E_3 TR_E_A2_OUT TR_E_A2_IN TR_E_A1_OUT TR_E_A1_IN ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 11 Main control register 2 OFFSET NAME (HEX) Mask word 100 M15 to M00 Control word 100 RPS_SIG4 RPS_SIG3 RPS_SIG2 RPS_SIG1 RPS_SIG0 UPLD_D1_B UPLD_D1_A UPLD_BRS UPLD_HPS_H UPLD_HPS_V UPLD_DMA3 UPLD_DMA2 UPLD_DMA1 UPLD_DEBI ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4 Register Programming Sequencer (RPS) The RPS is used as an additional method to program or read the registers of the SAA7146A. Its main function is programming the registers on demand without delay via the interrupt handler of the host system. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4.3 C OMMAND LIST An instruction list of an RPS task is built in the system memory by the device driver. This list is made up of command sequences; each command being at least one Dword long. The first Dword of a command consists of the instruction code (4-bit) and a command specific part (28 bits) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4.4.7 INTERRUPT The INTERRUPT command will set the RPS_I bit of the task in the Interrupt status register (see Table 41 executed and the condition described by the event flags is true. The execution of RPS continues. The format of the Interrupt command is shown in Tables 24 and 25 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1998 Apr 09 38 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1998 Apr 09 39 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1998 Apr 09 40 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4.4.10 LDREG and STREG The Load Register (LDREG) command has a variable Dword count specified by the Block_length least two Dwords long and at maximum 256 Dwords. The LDREG command interprets the following Dwords as data and writes it to the registers beginning at the specified register address (D6 to D0) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4.4.11 MASKLOAD The MASKLOAD command is a three Dword command. Its purpose is to modify only portions or selected bits of a SAA7146A register. The first Dword of the command contains the instruction code and specifies the register to be modified ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 34 RPS page register OFFSET NAME (HEX) C4 RPS_PAGE0 ERPSP0 C8 RPS_PAGE1 ERPSP1 7.4.7 L INE COUNTER THRESHOLDS For the events related to the line counters of the source and the target, (either HPS or BRS) there are two thresholds for each task in the HBI threshold register (see Table 35) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.4.8 RPS TIME OUT VALUE These registers contain the values for the time out conditions of the PAUSE and CHECK_LATE commands for each task. If the selected counter value is zero, the time out generation is disabled. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.5 Status and interrupts 7.5.1 G ENERAL In order to control the SAA7146A, the status information is collected and stored in two status registers: Primary Status Register (PSR) and Secondary Status Register (SSR). These two registers follow a hierarchical approach because the PSR contains summed up information from the SSR ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 110 RPS_TO0 21 UPLD 20 DEBI_S 19 DEBI_E 18 IIC_S 17 IIC_E 16 A2_in 15 A2_out 14 A1_in 13 A1_out 12 AFOU 11 V_PE 10 VFOU 9 1998 Apr 09 TYPE DESCRIPTION R RPS time out error in Task 0: this bit is set when the RPS Task 0 stays longer than expected in the WAIT state ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 110 FIDA 8 FIDB 7 PIN3 6 PIN2 5 PIN1 4 PIN0 3 ECS 2 EC3S 1 EC0S 0 Table 39 Secondary status register OFFSET NAME BIT (HEX) 114 PRQ 31 PMA 30 RPS_RE1 29 RPS_PE1 28 RPS_A1 27 1998 Apr 09 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 114 RPS_RE0 26 RPS_PE0 25 RPS_A0 24 DEBI_TO 23 DEBI_EF 22 IIC_EA 21 IIC_EW 20 IIC_ER 19 IIC_EL 18 IIC_EF 17 V3P 16 V2P 15 V1P 14 VF3 13 1998 Apr 09 TYPE R RPS Task 0 Register access Error: this bit is set when the LDREG, STREG or MASKWRITE command tries to access a non-existing register ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 114 VF2 12 VF1 11 AF2_in 10 AF2_out 9 AF1_in 8 AF1_out 7 6 VGT 5 LNQG 4 EC5S 3 EC4S 2 EC2S 1 EC1S 0 1998 Apr 09 TYPE R Video FIFO 2 underflow/overflow: this bit is set when the video FIFO 2 has an overfl ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 40 Interrupt enable register OFFSET NAME (HEX) DC PPEF PABO PPED RPS_I1 RPS_I0 RPS_late1 RPS_late0 RPS_E1 RPS_E0 RPS_TO1 RPS_TO0 UPLD DEBI_S DEBI_E IIC_S IIC_E A2_in A2_out A1_in A1_out AFOU V_PE VFOU ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 41 Interrupt status register OFFSET NAME BIT (HEX) 10C PPEF 31 PABO 30 PPED 29 RPS_I1 28 RPS_I0 27 RPS_late1 26 RPS_late0 25 RPS_E1 24 RPS_E0 23 RPS_TO1 22 RPS_TO0 21 UPLD 20 DEBI_S 19 DEBI_E 18 IIC_S 17 IIC_E 16 A2_in 15 A2_out 14 A1_in 13 A1_out 12 AFOU ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.6 General Purpose Inputs/Outputs (GPIO) 7.6.1 G ENERAL The SAA7146A has four general purpose I/O pins. For example, they could be used to signal to other devices a power-down mode or to map an internal status bit to it, e.g. to detect a sync lost from the VBLK pin of the SAA7110. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 45 Event Counter set 2 Register (EC2R) OFFSET NAME BIT (HEX) 11C EC5 [9: EC4 [9: EC3 [11: Table 46 Event Counter set 1 Source Select Register 1 (EC1SSR) OFFSET NAME BIT (HEX ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) ADDRESS STATUS BIT (HEX) 04 RPS_I0 05 RPS_LATE1 06 RPS_LATE0 07 RPS_E1 08 RPS_E0 09 RPS_TO1 0A RPS_TO0 0B UPLD 0C DEBI_S 0D DEBI_E 0E IIC_S 0F IIC_E 10 A2_in 11 A2_out 12 A1_in 13 A1_out 14 AFOU 15 V_PE 16 VFOU 17 FIDA 18 FIDB 19 PIN3 1A PIN2 1B PIN1 1C PIN0 1D ECS ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) ADDRESS STATUS BIT (HEX) 2C IIC_ER 2D IIC_EL 2E IIC_EF 2F V3P 30 V2P 31 V1P 32 VF3 33 VF2 34 VF1 35 AF2_in 36 AF2_out 37 AF1_in 38 AF1_out 39 3A VGT 3B LNQG 3C EC5S 3D EC4S 3E EC2S 3F EC1S Table 49 Event Counter Threshold set 1 Register (ECT1R) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 50 Event Counter Threshold set 2 Register (ECT2R) OFFSET NAME (HEX) F0 ECT6 [9: ECT5 [9: ECT4 [11: Note 1. Each of these threshold values shows the limit up to which the related counter will run before it sets it interrupt status bit ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.8.2 DD1 (CCIR 656, SMPTE125M), I/O UAL 7.8.2.1 Cb-Y-Cr-Y 8-bit wide stream In this mode two video ports with YUV sampling scheme are available. Each D1 port has an I/O capability and has a separate clock input and separate sync lines. In this format the pixel rate is equivalent to the clock rate LLC. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.8.2.2 YUV 16-bit parallel (DMSD2) stream In this mode only the HPS data path is available since the BRS data path supports only 8-bit wide data streams. Colour difference signal and luminance signal (straight binary) are available in parallel on a 16-bit wide data stream. In this mode both D1 ports are inputs (see Fig ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth LLC PXQ_x D1_x ( PXQ_x D1_x ( Fig.11 Timing of PXQ_x for CCIR 656 at the D1_x port. Table 51 Video timing reference codes BYTE 7 (MSB) First 1 Second 0 Third ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 52 Protection bits BIT NUMBER FIXED 7.8.5 S YNCHRONIZATION SIGNALS Horizontal, vertical and frame synchronization signals are either carried beside the data stream on the extra sync ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 53 Field interval definitions for D1 (CCIR 656) SAV and EAV codes; note 1 DEFINITION V-digital field blanking Field 1; start ( Field 1; finish ( Field 2; start ( Field 2; finish ( F-digital field identification Field 1 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth LLC HS VS FLD V-DMSD FLD-DMSD Fig.13 Timing of field detection ODD-to-EVEN for direct mode. 7.8.7 A CQUISITION CONTROL The processing window for the scaling unit is defined in the acquisition control. The internal counters (one for the HPS and one for the BRS) receives programmable values for offset (HXO11 to HXO0, HYO11 to HYO0 and BXO9 to BXO0, BYO9 to BYO0) and length (NumLines, NumBytes) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth ( qualified lines, i.e. lines containing at least one qualified pixel. 7.8.8 C CCIR 656 OMPARISON BETWEEN This section describes how to choose the vertical offset and how to use the source line counter event for RPS programming for capturing the expected line ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 54 Offsets to CCIR 656 line 23 depending on PAL or NTSC source (in compliance with Recommendation 601), ODD and EVEN field and select mode (see note 1) PAL (2) (3) SLC SLC ext. SAV/EAV FS 24 (25) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth FID CCIR 656 VS CCIR 656 ODD SAA711x VS SAA711x LINES (1) 621 622 (2) (308) (309) (310) (1) The line numbers not in parenthesis refer to CCIR counting. (2) The line numbers in parenthesis refer to single field counting. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1998 Apr 09 66 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.8.8.2 Video with NTSC format handbook, full pagewidth FID CCIR 656 VS CCIR 656 ODD SAA711x VS SAA711x LINES (1) 523 524 525 (2) (260) (261) (262) (1) The line numbers not in parenthesis refer to CCIR counting. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 1998 Apr 09 68 Product specification SAA7146A ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.9 High Performance Scaler (HPS) Depending on the selected port modes the incoming and scaled data are formatted/reformatted (8-bit or 16-bit), and the corresponding reference signals are generated. Based on these reference signals the active processing window is defined in a versatile way via programming ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) The subsampler collects a number of [XPSC + 2 pixels to calculate a new subsampled output pixel downscale dependent FIR filter is built with taps which reduces anti-aliasing for small sizes. If XACM = 0, the collecting sequence overlaps which means that the last pixel of sequence M is also the first pixel of sequence ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 18 handbook, full pagewidth 0.1 Fig.20 Chrominance Prefilter: frequency response for miscellaneous register settings. Table 57 Horizontal prescaling and normalization HORIZONTAL XPSC PRESCALER SEQUENCE (EXAMPLE ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) HORIZONTAL XPSC PRESCALER SEQUENCE (EXAMPLE 1121 1211 1111 1111 1 10 1111 111 111 1111 13 1111 211 112 1111 1111 112 211 1111 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.9.2.4 Vertical scaler The vertical scaler performs the vertical downscaling of the input data stream to a randomly number of output lines. It can be used for input line lengths up to 768 pixels/line and has to be bypassed, if the input line length exceeds this pixel count ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 58 Vertical scaling and normalization VERTICAL COEFFICIENT SCALE YACL SEQUENCE (EXAMPLE) RATIO ( (512 (683 (768 (820) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) VERTICAL COEFFICIENT SCALE YACL SEQUENCE (EXAMPLE) RATIO 1111 1111 1 1 1111 1111 17 18 (964) 2212 2212 2 2 2122 2122 1222 2222 1 1 2222 2221 ... ... 1111 2222 1111 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.9.3 H ORIZONTAL PHASE SCALING In the phase correct Horizontal Phase Scaling (HPS) the pixels are calculated for the geometrically correct, orthogonal output pattern, down to pattern. A horizontal zooming feature is also supported. The maximum zooming factor is at least 2, even more dependent on input pattern and prescaling settings ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth 1 1/2 line dropping handbook, full pagewidth 1 line repetition 1998 Apr 09 D1 vertical downscaling 1/4 PCI (DMA3) Fig.23 BRS inbound mode. D1 vertical 4 upscaling 2 PCI (DMA3) Fig.24 BRS outbound mode 1/2 horizontal ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) The PCI source data is defined by the base address (BaseOdd3 and BaseEven3), the distance between the start addresses of two consecutive lines of a field (Pitch3), the number of lines per field of the source frame (NumLines3) and the number of bytes per line of the source frame (NumByte3) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth Fig.26 Reference signals for scaling window for direct and line memory mode. 7.10.2.2 Direct mode The timing reference signals (VS, HS, LLC and FID) are taken from port A or port B. The BRS has to deliver pixel ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth Fig.27 Sync and data path for direct and line memory mode. 7.10.3 VBI DATA INTERFACE The SAA7146A transports VBI data (data during the Vertical Blanking Interval) or VBI test signals between real time world and the computer system ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 59 RGB-32 format BIT 31 TO BIT Table 60 RGB-24 packed format BUS CYCLE BIT 31 TO BIT The following formats use two pixels per Dword and derive RGB from RGB-24 by truncation or by error diffusion dither. The byte phase of the first sample each line is defined by LSB + 1 of DMA base. ‘ ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 62 YUV format BIT 31 TO BIT Table 63 YUV format BUS CYCLE BIT 31 TO BIT The following formats are planar YUV formats and use the three video FIFOs and three video DMA Channels 1, 2 and 3. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.11.2 B INARY RATIO SCALER OUTPUT FORMATS All YUV formats are based on CCIR coding: Luminance Y in straight binary: Black 256 linear coding White 235 of 256 linear coding. Colour difference signals UV in offset binary: No colour 128 of 256 steps Full colour 128 112 steps ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 66 Initial setting of Dual D1 interface OFFSET NAME BIT (HEX) 50 LLC_A 31 SIO_A PVO_A 28 PHO_A 27 50 SYNC_A FIDESA 23 and 1998 Apr 09 TYPE RW Line Locked Clock control for D1_A: ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 50 LLC_B 15 50 SIO_B 14 and 13 50 PVO_B 12 50 PHO_B 11 50 SYNC_B FIDESB 7 and 1998 Apr 09 TYPE RW Line Locked Clock control for D1_B: 0: LLC_B set to input ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.12.2 V IDEO DATA STREAM HANDLING AT PORT Table 67 Video data stream handling at port D1_A OFFSET NAME BIT (HEX) 54 VID_A 31 and 30 Y8C_A 29 28 and 27 PFID_A 7.12.3 V IDEO DATA STREAM HANDLING AT PORT Table 68 Video data stream handling at port D1_B ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.12.4 BRS P R ROGRAMMING EGISTER The BRS programming has in principle three modes: 1. Inbound and downscaling: the binary ratio scaler input multiplexer selects data from the Dual D1 real time video interface, Port and ‘normally’ writes the result via FIFO 3 and DMA3 to PCI, if DMA3 is enabled in master write mode and not used for other purposes ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME BIT (HEX) 58 BXO BRS_H Read mode 3 and 2 PCI format 1 and 0 1998 Apr 09 TYPE INBOUND RW horizontal offset, counted in qualified LLC cycles, after selected horizontal sync edge, till ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 70 Horizontal offset values for the field memory mode RATIO 7.12.5 HPS PROGRAMMING REGISTER Table 71 HPS control register OFFSET NAME BIT (HEX) 5C HPSdatasel 31 and 30 Mirror 29 HPSsyncsel HYO ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.12.6 V ERTICAL AND HORIZONTAL SCALING Table 72 HPS, vertical scaling OFFSET NAME BIT (HEX) 60 YACM 31 YSCI YACL YPO YPE 1998 Apr 09 TYPE RW Y (vertical) scaler Accumulation (calculation) Mode of vertical ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 73 HPS, vertical scale and gain OFFSET NAME BIT (HEX) 64 PFY PFUV DCGY CYA CYB Table 74 Prefilter selection for luminance component Y PFY1 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 75 Prefilter selection for colour difference signals UV PFY1 PFY0 Table 76 DC gain control of Y scaler DCGY2 DCGY1 Table 77 Weight factor as a function of CYi and DCGY ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 79 HPS, horizontal prescaler OFFSET NAME BIT (HEX and 30 DCGX XPSC XACM 17 16 CXY CXUV Table 80 Selection of output gain DCGX2 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 81 HPS, horizontal fine-scale OFFSET NAME BIT (HEX) 6C XIM XSCI HXO 7.12.7 BCS Table 82 BCS control OFFSET NAME BIT (HEX) 70 BRIG CONT SATN ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 85 Chrominance saturation control 7.12.8 C HROMA KEY Table 86 Chroma key range OFFSET NAME BIT (HEX 1998 Apr 09 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 87 HPS output and formats OFFSET NAME BIT (HEX) 78 matrix 31 and 30 29 and 28 outformat and 22 21 and 20 SHIFT 17 DITHER 16 Table 88 Output formats CODE (HEX) 0 YUV ( YUV composed, ‘packed’ ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 89 Clip control OFFSET NAME BIT 78H ClipCK 9 and 8 7 ClipMode RecInterl 3 2 ClipOut 1 and 0 7.13 Scaler event description The RPS is controlled by the PAUSE command on special events. This section describes the video events. Because of these video events a defined time for an upload is given ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 90 UPLOAD handling for the scaler registers OFFSET REGISTER (HEX) Initial setting of Dual 50 D1 Interface Video DATA stream 54 handling at port D1_A Video DATA stream 54 handling at port D1_B BRS control register ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.14 Clipping The SAA7146A supports clipping in the HPS data path. Clipping can be achieved with the chroma key information or with clip data information coming via master read through FIFO 2. Both sources will be OR-ed and can be switched on/off or inverted individually ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth handbook, full pagewidth 7.14.2.1 Memory organization for rectangle overlay windows. Every overlay window is defined by two corners with four coordinates. One Dword holds one 11-bit coordinate and 16-bit with the display information for overlay windows ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) The two lists, pixel list and line list, are interlocked in the 64 Dword memory. The pixel list is located at the even addresses, the line list at the odd addresses. This organization reduces the number of Dwords to be loaded, if there are less then 16 overlay windows ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.15.4 F UNCTIONAL DESCRIPTION An immediate access cycle consists of one address phase and one data phase. A block transfer with address increment enabled consists of several consecutive address/data phase couples. A block transfer with disabled address increment consists of one address phase followed by several data phases ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.15.4.1 Target bus cycle in Intel mode The SAA7146A starts a target transfer cycle by placing the target address on the multiplexed address/data lines (AD15 to AD0). The Address Latch Enable (ALE) is then asserted (set LOW) indicating that the address lines ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) address phase handbook, full pagewidth t as AD(WR) AD(RD) SBHE ALE RDN WRN RDY Fig.32 Intel style block transfer without address increment. 7.15.4.2 Target bus cycle in Motorola mode The target transfer cycle starts with applying the target address onto the multiplexed address/data lines ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) address phase handbook, full pagewidth t as AD(WR) address AD(RD) address RWN AS UDS LDS DTACK address phase handbook, full pagewidth t as AD(WR) address AD(RD) address RWN AS UDS LDS DTACK Fig.34 Motorola style block transfer without address increment. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 93 Timing parameters (t PCI SYMBOL PARAMETER t address set-up time as t address hold time ah t delay between de-asserting of RDN/WRN alh and ALE t address 3-state time before start of read az command t write data output hold time ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.15.4.3 Transfer configuration When using ‘dumb’ targets (unable to handshake) or ‘slow’ targets (unable to pull DTACK_RDY immediately), the cycle length is adjusted by using a programmable cycle timer. At TIMEOUT in Motorola mode the transfer control gets into a defined state by finishing the cycle when a slave is hanging or not able to handshake ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth AD(WR) AD(RD) SBHE ALE RDN WRN CLK Fig.35 PCI clock related protocol scheme for non-increment Intel mode, no access stretching via RDY. handbook, full pagewidth AD(WR) address AD(RD) address SBHE ALE RDN ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 94 Overview of peak data rates for non-increment (burst) block transfer configurations at 33 MHz PCI clock PROTOCOL TIMEOUT MODE VALUE (2) Intel/Motorola 0 (2) Intel/Motorola 0 Intel/Motorola 1 Intel/Motorola 3 (2) Intel/Motorola 0 Intel/Motorola 1 Note 1. These peak data rates could be reached for transfers with large BLOCKLENGTH settings well performing PCI-bus system with low bus load and an appropriate target system without cycle stretching or interrupts ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.15.4.4 Command word description To configure and initiate a transfer there are 3 PCI memory mapped command words. A DEBI register upload after writing to DEBI_COMMAND starts the transfer process. Table 95 DEBI_CONFIG OFFSET NAME 7CH XIRQ_EN ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16 Audio interface 7.16.1 G ENERAL DESCRIPTION The SAA7146A has two independent audio interface circuits (A1 and A2) for serial input and output of digital audio data streams. The audio interface circuits are based 2 on the I ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.3 A UDIO INTERFACE PINS There are 14 audio interface pins. SD1 is output only for A1 and input only for A2, SD4 is output only for A2 and input only for A1. The other pins can be used by either one of the two interface circuits but only one at a time. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.4.1 Audio clock selection The clock divider circuit offers 16 different clock stages. To transform a reference clock of 24.576 MHz to a bit clock for an 8 kHz and 8-bit sampling (just 8-bit serial), a clock division of 384 has to be selected. To transform a reference clock of 24 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.4.2 Audio data path Figure 40 illustrates the audio data path. An input multiplexer selects serial data from one of four SD pins. A1 can select SD0 and the common serial data pins SD1, SD2 and SD3. A2 can select SD4 and the common serial data pins SD1, SD2 and SD3 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 100 Feedback buffers OFFSET NAME 144H FB_BUFFER1 148H FB_BUFFER2 Under control of the time slot list, a collected Dword is then stored into the input FIFO. The FIFO size is determined to 24 Dwords. ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Each interface, A1 and A2, uses its own Time Slot List (TSL) when working independently of each other. The shaded areas are valid for combined processing of TSL1 and TSL2 only. In these modes, TSL1 or TSL2 are used interleaved or concatenated, to achieve one single TSL with records ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 102 Time slot list bit functions NAME WS0 defining pattern of word select signal output at WS0 pin; if WS0 pin is input and trigger, WS0 bit is meaningless WS1 defining pattern of word select signal output at WS1 pin WS2 defi ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.5 A UDIO CONFIGURATION The configuration parameters are selected using two configuration registers, ACON1 and ACON2. The ACON1 register is locally buffered. The download from the shadow register into the working register is performed when a DMA protection address is reached or immediately when both interfaces are not active (switched off, initial state). Table 103 Audio Confi ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.5.1 Audio mode control There are 3 audio mode bits to select which TSL is active and how to synchronize and combine them. The first half of Table 105 supports asynchronous operation of A1 and A2, each following their own configuration bits and working independent of each other ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.5.2 Audio input level monitoring The audio input level monitoring feature allows the control of audio input levels without additional external hardware, by comparing the absolute value of the most significant byte of an audio sample to a programmable reference maximum level ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.16.5.4 Bit clock control Specific to each audio interface A2, is the programming of bit clock source. Table 109 CLK source definition AX_CLKSRC [4:0] (HEX reserved 12 ACLK divided-by-384 11 ACLK divided-by-256 10 ACLK divided-by-192 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 2 7.17 I C-bus interface 7.17.1 G ENERAL DESCRIPTION 2 The I C-bus is a simple 2-wire bus for efficient inter-IC data exchange. Only two bus lines are required: a serial clock line (SCL) and a serial data line (SDA). It’s a true ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 110 Status register (IICSTA); note 1 OFFSET NAME (HEX) 90 IICCC [2: ABORT SPERR APERR DTERR DRERR AL ERR BUSY Note 1. The error bits have to be cleared, before a new command can be executed. This may be needed twice after using ABORT ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 112 Transfer control register (IICTRF) OFFSET NAME (HEX) 8C BYTE2 BYTE1 BYTE0 ATTR2 [1:0] ATTR1 [1:0] ATTR0 [1:0] ERR BUSY Table 113 ATTRx1 and ATTRx0; attribute information for BYTEx ATTRx1 ATTRx0 SYMBOL 1 1 START ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.17.2.2 Example The protocol sequence for reading three bytes with subaddress access is illustrated in Fig.43. The procedure for this read operation is detailed below: 1. Address slave, write to IICTFR (see Fig.44): BYTE2 [7:1] = DA, BYTE2 [ (write), ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, halfpage handbook, halfpage Fig.45 Transfer data and write attribute information to IICTFR. 1998 Apr Fig.44 Address slave and write to IICTFR MGD698 126 Product specification ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 7.18 SAA7146A register tables Table 114 Registers and offsets sorted by functional groups OFFSET NAME (HEX) 00 BaseOdd1 04 BaseEven1 08 ProtAddr1 0C Pitch1 10 BasePage1 14 Num_Line_Byte1 18 BaseOdd2 1C BaseEven2 20 ProtAddr2 24 Pitch2 28 BasePage2 2C Num_Line_Byte2 30 BaseOdd3 34 BaseEven3 38 ProtAddr3 3C Pitch3 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME (HEX) 134 PCI_ADP3 138 PCI_ADP4 13C PCI_DDP FC MC1 100 MC2 104 RPS_ADDR0 108 RPS_ADDR1 C4 RPS_PAGE0 C8 RPS_PAGE1 CC RPS_THRESH0 D0 RPS_THRESH1 D4 RPS_TOV0 D8 RPS_TOV1 110 PSR 114 SSR DC IER 10C ISR E0 GPIO_CTRL ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME (HEX) 88 DEBI_AD 7C DEBI_CONFIG 80 DEBI_COMMAND 84 DEBI_PAGE F4 ACON1 F8 ACON2 144 FB_BUFFER1 148 FB_BUFFER2 140 LEVEL_REP 180-1BC audio time slot registers 1 1C0-1FC audio time slot registers 2 Table 115 Registers and offsets sorted by address-offset ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME (HEX) 60 HPS, vertical scale 64 HPS, vertical scale and gain 68 HPS horizontal prescale 6C HPS horizontal fine-scale 70 BCS control 74 chroma key range 78 HPS output and formats clip control 7C DEBI_CONFIG ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) OFFSET NAME (HEX) FC MC1 100 MC2 104 RPS_ADDR0 108 RPS_ADDR1 10C ISR 110 PSR 114 SSR 118 EC1R 11C EC2R 120 PCI_VDP1 124 PCI_VDP2 128 PCI_VDP3 12C PCI_ADP1 130 PCI_ADP2 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Table 116 BST instructions supported by the SAA7146A INSTRUCTION BYPASS this mandatory instruction provides a minimum length serial path (1-bit) between TDI and TDO when no test operation of the component is required EXTEST this mandatory instruction allows testing of off-chip circuitry and board level interconnections ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 9 ELECTRICAL OPERATING CONDITIONS Operating time: the circuit is designed to be able to operate continuously Backup: no backup capability (standby) will be provided internally Handling: inputs and outputs are protected against electrostatic discharge in normal handling. However totally safe desirable to take normal handling precautions appropriate to handling MOS devices ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PARAMETER t output fall time from V o(f) V with a bus capacitance ILmax from 10 to 400 pF I input current each I/O pin with an i input voltage between 0.4 and 0.9V DDi2Cmax C capacitance for each I/O pin i Clock input timing (LLC_A and LLC_B) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SYMBOL PARAMETER C input pin capacitance i C CLK pin capacitance CLK C IDSEL pin capacitance IDSEL AC SPECIFICATION I switching current HIGH OH test point I switching current LOW OL test point t output rise slew rate slew(r) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) Notes 1. Input leakage currents include high-impedance output leakage for all bidirectional buffer with 3-state outputs. 2. Levels measured with load circuit: 1 (TTL load) and C 3. Voltage of the V sense pin is defined as V ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth clock input LCC_(A, B) data and control inputs input PXQ_(A, B) data and control outputs clock output LLC_(A, B) 1998 Apr 09 t LLC t LLCH not valid t pd ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) handbook, full pagewidth CLK OUTPUT DELAY 3-STATE OUTPUT INPUT 1998 Apr 09 1 val 1 off 1.5 V input valid 1.5 V Fig.48 PCI I/O timing. 138 Product specification SAA7146A 2.4 V 0.4 V 2.4 V 0.4 V MGG280 ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 11 APPLICATION EXAMPLE handbook, full pagewidth analog audio SAA7360/66 antenna PHILIPS TUNER analog video NTSC, PAL 1998 Apr YUV C-bus MPEG, SAA7111A I/O SAA7146A FRONT END M-JPEG DECODER ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 12 PACKAGE OUTLINES QFP160: plastic quad flat package; 160 leads (lead length 1.95 mm); body 3.4 mm; high stand-off height y 120 121 pin 1 index 160 DIMENSIONS (mm are the original dimensions) ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 3 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 13 SOLDERING 13.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...
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... Philips Semiconductors Multimedia bridge, high performance Scaler and PCI circuit (SPCI) 14 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...