FW323-05 Agere Systems, FW323-05 Datasheet
FW323-05
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FW323-05 Summary of contents
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Features 1394a-2000 OHCI link and PHY core function in sin- gle device: — Enables smaller, simpler, more efficient mother- board and add-in card designs by replacing two components with one — Enables lower system costs — ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Contents Features ...................................................................................................................................................................1 FW323 Functional Overview ....................................................................................................................................7 Other Features ......................................................................................................................................................... 7 FW323 Functional Description ........................................................................................................................... 7 PCI Core ............................................................................................................................................................7 Isochronous Data Transfer ................................................................................................................................ 8 Asynchronous Data Transfer .............................................................................................................................8 Asynchronous Register ...................................................................................................................................... 8 Serial EEPROM Interface ..................................................................................................................................9 Link Core ............................................................................................................................................................9 PHY Core ........................................................................................................................................................... 9 Pin Information ....................................................................................................................................................... 13 Application Schematic ............................................................................................................................................ 18 Internal Registers ...................................................................................................................................................20 PCI Configuration Registers ...
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... TQFP ................................................................................................................................................ 150 Figure Figure 1. FW323 Functional Block Diagram .............................................................................................................7 Figure 2. PHY Core Block Diagram ........................................................................................................................ 12 Figure 3. Pin Assignments for FW323 .................................................................................................................... 13 Figure 4. Application Schematic for FW323 ........................................................................................................... 19 Figure 5. Bus Timing ............................................................................................................................................ 142 Figure 6. Write Cycle Timing ................................................................................................................................ 142 Figure 7. Data Validity .......................................................................................................................................... 142 Figure 8. Start and Stop Definition ....................................................................................................................... 143 Figure 9 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Table Table 1. Pin Descriptions ........................................................................................................................................14 Table 2. Bit-Field Access Tag Description ..............................................................................................................20 Table 3. PCI Configuration Register Map ...............................................................................................................20 Table 4. Vendor ID Register ...................................................................................................................................21 Table 5. Device ID Register ....................................................................................................................................22 Table 6. PCI Command Register ............................................................................................................................23 Table 7. PCI Command Register Description .........................................................................................................24 Table 8. PCI Status Register ..................................................................................................................................25 Table 9 ...
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... Table 99. Physical Request Filter High Register Description ...............................................................................114 Table 100. Physical Request Filter Low Register ................................................................................................116 Table 101. Physical Request Filter Low Register Description ..............................................................................117 Table 102. Asynchronous Context Control Register ............................................................................................119 Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Table of Contents (continued) FW323 05 Page 5 ...
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... Table 114. Isochronous Receive Context Match Register ...................................................................................131 Table 115. Isochronous Receive Context Match Register Description ................................................................132 Table 116. FW323 Vendor Specific Registers Description ...................................................................................133 Table 117. Isochronous DMA Control Registers Description ...............................................................................134 Table 118. Asynchronous DMA Control Registers Description ............................................................................135 Table 119 ...
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... V operation tolerant inputs 128-pin TQFP package The FW323 is the Agere Systems Inc. implementation of a high-performance, PCI bus-based open host controller for implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost- effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized ...
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... After processing each context, ITDMA writes a cycle marker word in the transmit FIFO to indicate to the link core that there is no more data for this isochronous cycle summary, the major steps for the FW323 ITDMA to transmit a packet are the following Fetch a descriptor block from host memory. ...
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... EEPROM. The interface consists of the ROM_AD and ROM_CLK pins. Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface ROM_CLK is an output clock provided by the FW323 to (continued) the external EEPROM. ROM_AD is bidirectional and is used for serial data/control transfer between the FW323 and the external EEPROM ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface FW323 Functional Description The PHY/link interface is a direct connection and does not provide isolation. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in syn- chronization with the 49 ...
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... FW323 Functional Description regardless of whether a cable is connected to port or not connected to a port. For those applications, when FW323 is used with one or more of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface FW323 Functional Description CPS LPS SYSCLK LREQ CTL0 LINK CTL1 INTERFACE I LINKON PC0 PC1 PC2 CONTENDER SE SM RESETN 12 12 (continued) RECEIVED DATA DECODER/ RETIMER ARBITRATION AND CONTROL STATE MACHINE ...
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... Figure 3. Pin Assignments for the FW323 FW323 05 102 VSSA 101 TPBIAS2 100 TPA2+ 99 TPA2– 98 TPB2+ 97 TPB2– 96 VDDA 95 VSSA 94 CPS 93 VDD LPS 90 LKON 89 PC0 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Pin Information (continued) Table 1. Pin Descriptions Pin Symbol* 1 VDD 2 VSS 3 CARDBUSN CNA 6 NANDTREE 7 TEST1 8 ROM_CLK 9 ROM_AD 10 TEST0 11 VDD 12 VSS 13 CLKRUNN 14 PCI_INTAN 15 PCI_RSTN 16 PCI_GNTN 17 PCI_REQN 18 PCI_PMEN 19 VDD 20 PCI_CLK 21 VSS 22 PCI_AD[31] 23 PCI_AD[30] 24 PCI_AD[29] 25 PCI_AD[28] ...
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... PCI Address/Data Bit. — Ground. I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. — Ground. — Power. I/O PCI Command/Byte Enable Signal (Active-Low). I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. — Ground. I/O PCI Address/Data Bit. FW323 05 Description 15 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* 79 PCI_AD[3] 80 PCI_AD[ PCI_AD[1] 84 PCI_AD[0] 85 PCI_VIOS 86 CONTENDER 87 PC2 88 PC1 89 PC0 90 LKON 91 LPS CPS 95 V SSA 96 V DDA 97 TPB2- 98 TPB2+ ...
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... Analog Circuit Ground. All V tied together to a low-impedance ground plane. — Analog Circuit Power. V analog portion of the device. FW323 05 Description signals should be SSA signals should be SSA supplies power to the DDA signals should be ...
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... The application schematic presents a complete three-port, 400 Mbits/s IEEE 1394a-2000 design, featuring the Agere FW323 PCI bus-based host OHCI controller and 400 Mbits/s PHY core. The FW323 device needs only a power source (U3), connection to PCI interface, 1394a-2000 terminators and connectors, crystal, and serial EEPROM ...
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... PCI_PRSTN INTA# 14 PCI_INTAN PME# 18 PCI_PMEN BPWR CR2 MBRS340T3 5 V PCI CR4 MBRS340T3 12 V PCI F4 1.5 A RESETTABLE Figure 4. Application Schematic for the FW323 Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface 3 121 24.576 MHz ...
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... PCI PHY/Link Open Host Controller Interface Internal Registers This section describes the internal registers in FW323, including both PCI configuration registers and OHCI regis- ters. All registers are detailed in the same format; a brief description for each register, followed by the register offset and a bit table describing the reset state for each register ...
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... Register: Vendor ID register Type: Read only Offset: 00h Default: 11C1h Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface FW323 05 21 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Device ID Register The device ID register contains a value assigned to the FW323 by Agere. The device identification for the FW323 is 5811h. Table 5. Device ID Register Field Bit Type Default Name 15 Device ...
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... October 2001 Internal Registers (continued) PCI Command Register The command register provides control over the FW323 interface to the PCI bus. All bit functions adhere to the definitions in the PCI local bus specification the following bit descriptions. Table 6. PCI Command Register Field ...
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... Address/Data Stepping Control. The FW323 does not support address/data stepping; thus, this bit is hardwired Parity Error Enable. When this bit is set, the FW323 is enabled to drive PERR response to parity errors through the PERR signal. R VGA Palette Snoop Enable. The FW323 does not feature VGA palette snooping ...
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... October 2001 Internal Registers (continued) PCI Status Register The status register provides status over the FW323 interface to the PCI bus. All bit functions adhere to the definitions in the PCI local bus specification the following bit descriptions. Table 8. PCI Status Register Field ...
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... Internal Registers (continued) Class Code and Revision ID Register The class code register and revision ID register categorizes the FW323 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is indicated in the lower byte. ...
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... Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the FW323. Table 11. Latency Timer and Class Cache Line Size Register ...
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... Table 12. Latency Timer and Class Cache Line Size Register Description Bit Field Name 15:8 LATENCY_TIMER 7:0 CACHELINE_SZ Header Type and BIST Register The header type and BIST register indicates the FW323 PCI header type, and indicates no built-in self-test. Table 13. Header Type and BIST Register Field Bit Type Name 15 BIST ...
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... PCI PHY/Link Open Host Controller Interface Type R Built-In Self-Test. The FW323 does not include a built-in self-test; thus, this field returns 00h when read. R PCI Header Type. The FW323 includes the standard PCI header, and this is communicated by returning 00h when this field is read. FW323 05 Description 29 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI con- trol. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4K bytes of mem- ory address space are required for the OHCI registers ...
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... OHCI Memory Type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. R OHCI Memory Indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped into system memory space. FW323 05 Description 31 ...
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... Internal Registers (continued) PCI Subsystem Identification Register The PCI subsystem identification register is used to uniquely identify the card or system in which the FW323 resides. These values are loaded from the serial EEPROM during the power-up sequence. Table 17. PCI Subsystem Identification Register Description Bit ...
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... RW RW Type R Interrupt Pin Register. This register returns 01h when read, indi- cating that the FW323 PCI function signals interrupts on the INTA pin. RW Interrupt Line Register. This register is programmed by the system and indicates to software to which interrupt line the FW323 INTA is connected. ...
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... Maximum Latency. The contents of this register may be used by host BIOS to assign an arbitration priority level to the FW323. The default for this register indicates that the FW323 may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial ROM ...
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... PCI PHY/Link Open Host Controller Interface Type Default FW323 05 35 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 24. PCI OHCI Control Register Description Bit Field Name 31:1 Reserved 0 GLOBAL_SWAP 36 36 Type R Reserved. Bits 31:1 return 0s when read. RW When this bit is set, all quadlets read from and written to the PCI inter- face are byte swapped ...
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... Type R Next Item Pointer. The FW323 supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. R Capability Identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power management capability ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Power Management Capabilities Register The power management capabilities register indicates the capabilities of the FW323 related to PCI power management. Table 27. Power Management Capabilities Register Field Bit Name 15 PME_D3COLD 14 PME_D3HOT 13 PME_D2 12 PME_D1 ...
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... Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type R PME Support from D3 COLD. Set to 0, indicating the FW323 will not generate a PME event in the D3 COLD state. R PME Support From D3 HOT. Set to 1, indicating that the FW323 can generate a PME event in the D3 HOT state. ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3 HOT to D0 state ...
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... Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RC This bit is set when the FW323 would normally be asserting the PME signal, independent of the state of the PME_ENB bit. This bit is cleared by a writeback of 1, and this also clears the PME signal driven by the FW323 ...
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... Power Management Data. This field returns 00h when read since the FW323 does not report dynamic data. R Power Management CSR Bridge Support Extensions. This field returns 00h when read since the FW323 does not provide P2P bridging. Data Sheet, Rev. 2 October 2001 ...
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... Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space. These registers are the primary interface for controlling the FW323 IEEE 1394 OHCI function. This section provides the register interface and bit descriptions. There are several set and clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 33. OHCI Register Map (continued) DMA Context Self-ID — Isochronous receive channel mask high Isochronous receive channel mask low — Asynchronous request filter high Asynchronous request filter low 44 44 Register Name ...
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... Context control Reserved Command pointer Reserved Context control Reserved Command pointer Reserved Context control Reserved Command pointer Context control Reserved Command pointer Context match FW323 05 Abbreviation Offset ContextControlSet 180h ContextControlClear 184h — 188h CommandPtr 18Ch — 190h—19Ch ContextControlSet 1A0h ContextControlClear 1A4h — ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) OHCI Version Register This register indicates the OHCI version support, and whether or not the serial ROM is present. Table 34. OHCI Version Register Field Bit Name 31 Reserved GUID_ROM 23 Version ...
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... PCI PHY/Link Open Host Controller Interface Type R Reserved. Bits 31:25 return 0s when read. R The FW323 sets this bit if the serial ROM is detected. If the serial ROM is present, then the Bus_Info_Block and chip configuration data is automatically loaded on hardware reset. Major Version of the OHCI. The FW323 is compliant with the 1394 R Open Host Controller Interface Specification ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) GUID ROM Register The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register is set. Table 36. GUID ROM Register Field Bit Name 31 addrReset ...
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... FW323 completes the reset, it clears this bit. R Reserved. Bits 30:26 return 0s when read. RSU A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared when the FW323 completes the read of the currently addressed GUID ROM byte. R Reserved. Bit 24 returns 0 when read. RU This field represents the data read from the GUID ROM and is only valid when rdStart = 0 ...
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... PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the FW323 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. Table 38. Asynchronous Transmit Retries Register Field ...
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... RW This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. FW323 05 Description 51 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) CSR Data Register The CSR data register is used to access the bus management CSR registers from the host through compare- swap operations. This register contains the data to be stored in a CSR if the compare is successful. ...
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... Data Sheet, Rev. 2 October 2001 Internal Registers (continued) Table 41. CSR Data Register Description Bit Field Name 31:0 csrData Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RWU At start of operation, the data to be stored if the compare is successful. FW323 05 Description 53 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host through compare- swap operations. This register contains the data to be compared with the existing value of the CSR resource. ...
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... Data Sheet, Rev. 2 October 2001 Internal Registers (continued) Table 43. CSR Compare Register Description Bit Field Name 31:0 csrCompare Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RW The data to be compared with the existing value of the CSR resource. FW323 05 Description 55 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) CSR Control Register The CSR compare register is used to access the bus management CSR registers from the host through compare- swap operations. This register contains the data to be compared with the existing value of the CSR resource. ...
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... Reserved 1:0 csrSel Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RU This bit is set by the FW323 when a compare-swap operation is complete reset whenever this register is written. R Reserved. Bits 30:2 return 0s when read. RW This field selects the CSR resource as follows BUS_MANAGER_ID ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset 48’hFFFF_F000_0400. Table 46. Configuration ROM Header Register Field Bit Name 31 info_length 30 29 ...
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... IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. IEEE 1394 Bus Management Field. Must be valid at any time RW bit 17 (linkEnable) of the host controller control register is set serial ROM is present, then this field is loaded from the serial ROM. FW323 05 Description 59 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus_Info_Block, 1394 addressable at FFFF_F000_0404. Table 48. Bus Identification Register Field Bit Name 31 busID ...
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... Data Sheet, Rev. 2 October 2001 Internal Registers (continued) Table 49. Bus Identification Register Description Bit Field Name 31—0 busID Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type R Contains the constant 32’h31333934, which is the ASCII value for 1394. FW323 05 Description 61 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block, 1394 addressable at FFFF_F000_0408. Table 50. Bus Options Register Bit Field 31 irmc 30 cmc 29 isc 28 bmc 27 pmc 26 Reserved 25 24 ...
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... Generation Counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. R Reserved. Bits 5:3 return 0s when read. R Link Speed. This field returns 010, indicating that the link speeds of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s are supported. FW323 05 Description 63 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third quadlet in the Bus_Info_Block 1394 addressable at FFFF_F000_0410. This register contains node_vendor_ID and chip_ID_hi fields ...
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... Register: GUID high register Type: Read only Offset: 24h Default: 0000 0000h Table 53. GUID High Register Description Bit Field Name 31:8 node_vendor_ID 7:0 chip_ID_hi Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type R IEEE 1394 Bus Management Fields. R FW323 05 Description 65 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) GUID Low Register The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to chip_ID_lo in the Bus_Info_Block 1394 addressable at FFFF_F000_0414. This register initializes hardware reset and behaves identical to the GUID high register ...
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... Data Sheet, Rev. 2 October 2001 Internal Registers (continued) Table 55. GUID Low Register Description Bit Field Name 31:0 chip_ID_lo Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type R IEEE 1394 Bus Management Fields. FW323 05 Description 67 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. Table 56. Configuration ROM Mapping Register ...
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... PCI PHY/Link Open Host Controller Interface Type quadlet read request to 1394 offset 48’hFFFF_F000_0400 through offset 48’hFFFF_F000_07FF is received, then the low- order 10 bits of the offset are added to this register to determine the host memory address of the read request. R Reserved. Bits 9:0 return 0s when read. FW323 05 Description 69 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Posted Write Address Low Register The posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 58. Posted Write Address Low Register ...
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... October 2001 Internal Registers (continued) Table 59. Posted Write Address Low Register Description Bit Field Name 31:0 offsetLo Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RU The lower 32 bits of the 1394 destination offset of the write request that failed. FW323 05 Description 71 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 60. Posted Write Address High Register ...
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... Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RU This field is the bus and node number of the node that issued the write request that failed. RU The upper 16 bits of the 1394 destination offset of the write request that failed. FW323 05 Description 73 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Vendor ID Register The vendor ID register holds the company organization that specifies any vendor-unique registers. Table 62. Vendor ID Register Field Bit Name 31 VendorUnique ...
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... Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type R Returns 0 when read, since the FW323 does not specify any vendor unique registers. R Returns 0 when read, since the FW323 does not specify any vendor unique registers. FW323 05 Description ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the OHCI portion of the FW323. Table 64. Host Controller Control Register Field Bit Name 31 Reserved 30 noByteSwapData ...
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... RSU When this bit is set, all FW323 states are reset, all FIFOs are flushed, and all OHCI registers are set to their hardware reset values unless otherwise specified. PCI registers are not affected by this bit ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) The self-ID buffer pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31:11 are read/write accessible. Table 66. Self-ID Buffer Pointer Register ...
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... Table 67. Self-ID Buffer Pointer Register Description Bit Field Name 31:11 SelfIDBufferPtr 10:0 Reserved Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Type RW Contains the 2 Kbyte aligned base address of the buffer in host memory where received self-ID packets are stored. R Reserved. FW323 05 Description 79 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Self-ID Count Register The self-ID buffer pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31:11 are read/write accessible. ...
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... This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23:16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0 when the self-ID reception begins. R Reserved. Bits 1:0 return 0s when read. FW323 05 Description 81 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register ...
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... If bit 4 is set, iso channel number 36 is enabled. If bit 3 is set, iso channel number 35 is enabled. If bit 2 is set, iso channel number 34 is enabled. If bit 1 is set, iso channel number 33 is enabled. If bit 0 is set, iso channel number 32 is enabled. FW323 05 83 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. Table 72. Isochronous Receive Channel Mask Low Register ...
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... If bit 4 is set, iso channel number 4 is enabled. If bit 3 is set, iso channel number 3 is enabled. If bit 2 is set, iso channel number 2 is enabled. If bit 1 is set, iso channel number 1 is enabled. If bit 0 is set, iso channel number 0 is enabled. FW323 05 85 ...
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... Interrupt Event Register The interrupt event set/clear register reflects the state of the various FW323 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write the corresponding bit in the clear register ...
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... R Reserved. Bits 29:27 return 0s when read. RSCU The FW323 has received a PHY core register data byte which can be read from the PHY core layer control register. RSCU If bit 21 (cycleMaster) of the link control register is set, then this indicates that over 125 ms have elapsed between the start of sending a cycle start packet and the end of a subaction gap ...
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... Type RU Reserved. Bits 15:10 return 0s when read. RU Indicates that the FW323 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. RSCU Indicates that a host bus error occurred while the FW323 was trying to write a 1394 write request, which had already been given an ack_complete, into system memory ...
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... In all cases except masterIntEnable (bit 31), the enables for each interrupt event align with the interrupt event register bits (see Tables 74 and 75). This register is fully compliant with OHCI and the FW323 adds an OHCI 1.0 compliant interrupt function to bit 30. ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 77. Interrupt Mask Register Description Bit Field Name 31 masterIntEnable 30 vendorSpecific 29 Type RSCU Master Interrupt Enable. If this bit is set, then external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, then external interrupts are not generated, regard- less of the interrupt mask register settings ...
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... PCI PHY/Link Open Host Controller Interface Type Default RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X FW323 05 91 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Register: Isochronous transmit interrupt event register Type: Read/set/clear Offset: 90h set register 94h clear register (returns IsoXmitEvent and IsoXmitMask when read) Default: 0000 00XXh Table 79. Isochronous Transmit Interrupt Event Register Description ...
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... PCI PHY/Link Open Host Controller Interface Type Default RSC X RSC X RSC X RSC X RSC X RSC X RSC X RSC X FW323 05 93 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set ...
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... Isochronous receive context 3 caused the interrupt event register bit 7 (isochRx) interrupt. RSCU Isochronous receive context 2 caused the interrupt event register bit 7 (isochRx) interrupt. RSCU Isochronous receive context 1 caused the interrupt event register bit 7 (isochRx) interrupt. RSCU Isochronous receive context 0 caused the interrupt event register bit 7 (isochRx) interrupt. FW323 05 Description 95 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register is used to enable the isochRx interrupt source on a per- channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register ...
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... PCI PHY/Link Open Host Controller Interface Type Default FW323 05 97 ...
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... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 85. Fairness Control Register Description Bit Field Name Type 31:8 Reserved R Reserved. Bits 31:8 return 0s when read. 7:0 pri_req RW This field specifies the maximum number of priority arbitration requests for asyn- chronous request packets that the link is permitted to make of the PHY core during fairness interval ...
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... PCI PHY/Link Open Host Controller Interface Type Default FW323 05 99 ...
Page 100
... Set to 0, since the FW323 does not support an external cycle timer. RSCU When this bit is set, and the PHY core has notified the FW323 that it is root, the FW323 generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22. When this bit is cleared, the OHCI accepts received cycle start packets to main- tain synchronization with the node which is sending them ...
Page 101
... PCI PHY/Link Open Host Controller Interface Type Default RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU FW323 05 101 ...
Page 102
... Reserved R Reserved. Bits 26:16 return 0s when read. 15:6 busNumber RWU This number is used to identify the specific 1394 bus to which the FW323 belongs when multiple 1394-compatible buses are connected via a bridge. 5:0 NodeNumber RU This number is the physical node number established by the PHY core during self-identification automatically set to the value received from the PHY core after the self-identification phase ...
Page 103
... PCI PHY/Link Open Host Controller Interface Type Default RWU 0 RWU FW323 05 103 ...
Page 104
... Table 91. PHY Core Layer Control Register Description Bit Field Name Type 31 rdDone RU This bit is cleared the FW323 when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is set when a register transfer is received from the PHY core. 30:28 Reserved R Reserved. Bits 30:28 return 0s when read. 27:24 ...
Page 105
... The isochronous cycle timer register indicates the current cycle number and offset. When the FW323 is cycle master, this register is transmitted with the cycle start message. When the FW323 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference ...
Page 106
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Register: Isochronous cycle timer register Type: Read/write/update Offset: F0h Default: XXXX XXXXh Table 93. Isochronous Cycle Timer Register Description Bit Field Name Type 31:25 cycleSeconds RWU This field counts seconds [rollovers from bits 24:12 (cycleCount field)] ...
Page 107
... ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the FW323. All nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set. ...
Page 108
... Type 31 asynReqAllBuses RSC If this bit is set, then all asynchronous requests received by the FW323 from 30 asynReqResource62 RSC If this bit is set, then asynchronous requests received from node 62 on local 29 asynReqResource61 RSC If this bit is set, then asynchronous requests received from node 61 on local 28 asynReqResource60 RSC If this bit is set, then asynchronous requests received from node 60 on local ...
Page 109
... FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. bus are accepted by FW323. FW323 05 109 ...
Page 110
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per- node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register ...
Page 111
... FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. ...
Page 112
... FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. received by the FW323 from that node are accepted. ...
Page 113
... PCI PHY/Link Open Host Controller Interface Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 FW323 05 113 ...
Page 114
... RSC If this bit is set, requests received by the FW323 from local bus node 49 will be 16 physReqResource48 RSC If this bit is set, requests received by the FW323 from local bus node 48 will be 15 physReqResource47 RSC If this bit is set, requests received by the FW323 from local bus node 47 will be ...
Page 115
... RSC If this bit is set, requests received by the FW323 from local bus node 36 will be 3 physReqResource35 RSC If this bit is set, requests received by the FW323 from local bus node 35 will be 2 physReqResource34 RSC If this bit is set, requests received by the FW323 from local bus node 34 will be ...
Page 116
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Physical Request Filter Low Register The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handle the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register ...
Page 117
... RSC If this bit is set, requests received by the FW323 from local bus node 17 will be 16 physReqResource16 RSC If this bit is set, requests received by the FW323 from local bus node 16 will be 15 physReqResource15 RSC If this bit is set, requests received by the FW323 from local bus node 15 will be ...
Page 118
... RSC If this bit is set, requests received by the FW323 from local bus node 4 will be 3 physReqResource3 RSC If this bit is set, requests received by the FW323 from local bus node 3 will be 2 physReqResource2 RSC If this bit is set, requests received by the FW323 from local bus node 2 will be ...
Page 119
... PCI PHY/Link Open Host Controller Interface Type run RSCU R R RSU FW323 05 Default 119 ...
Page 120
... Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch. RU The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). RU The FW323 sets this bit to 1 when it is processing descriptors. ...
Page 121
... Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables the context by setting the asynchronous context control register bit 15 (run). Table 104. Asynchronous Context Command Pointer Register ...
Page 122
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Register: Asynchronous context command pointer register Type: Read/write/update Offset: 19Ch (ATRQ) 1ACh (ATRS) 1CCh (ATRQ) 1ECh (ATRS) Default: XXXX XXXXh Table 105. Asynchronous Context Command Pointer Register Description Bit Field Name ...
Page 123
... RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC run RSC R R RSU FW323 05 Default ...
Page 124
... Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch. RU The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). RU The FW323 sets this bit to 1 when it is processing descriptors. ...
Page 125
... The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7) ...
Page 126
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 109. Isochronous Transmit Context Command Pointer Register Description Bit Field Name 31:0 descriptorAddress 126 126 Type R Address of the context program which will be executed when a DMA context is started. Data Sheet, Rev. 2 ...
Page 127
... PCI PHY/Link Open Host Controller Interface Type RSC RSC RSCU RSC run RSCU R R RSU FW323 05 Default 127 ...
Page 128
... Software sets this bit to cause the FW323 to continue or resume descrip- tor processing. The FW323 clears this bit on every descriptor fetch. RU The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). RU The FW323 sets this bit to 1 when it is processing descriptors. ...
Page 129
... The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables an isochronous receive context by setting the isochronous receive context control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7) ...
Page 130
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 113. Isochronous Receive Context Command Pointer Register Description Bit Field Name 31:0 descriptorAddress 130 130 Type RWU Address of the context program which will be executed when a DMA context is started. Data Sheet, Rev. 2 ...
Page 131
... PCI PHY/Link Open Host Controller Interface Type Default FW323 05 131 ...
Page 132
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 115. Isochronous Receive Context Match Register Description Bit Field Name 31 tag3 30 tag2 29 tag1 28 tag0 27:25 Reserved 24:12 cycleMatch 11:8 sync 7 Reserved 6 tag1SyncFilter 5:0 channelNumber 132 132 Type RW If this bit is set, then this context matches on iso receive packets with a tag field of 11b ...
Page 133
... FW323 Vendor Specific Registers The FW323 contains a number of vendor-defined registers used for diagnostics and control low-level hardware functions. These registers are addressable in the upper 2K of the 4K region defined by PCI base address register 0 (registers defined by the OHCI specification reside in the lower 2K of this region). The control registers should not be changed when the link is enabled ...
Page 134
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Isochronous DMA Control The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO constraints, and the PCI cache line size ...
Page 135
... AR FIFO before the AR unit will request access to the PCI bus. For the physical write unit, this value defines the minimum PCI burst, packet size permitting. The threshold quadlets and defaults to 3 (64 quadlets). FW323 05 135 ...
Page 136
... Link Options The values in this register control the operation of the link module within the FW323 beyond what is stated in 1394 and OHCI specifications. In general, these controls are to be used for debugging and diagnostic purposes only and should not be modified from power reset default values. ...
Page 137
... OHCI GUIDLo[7:0] 0x1d OHCI GUIDLo[15:8] 0x1e OHCI GUIDLo[23:16] 0x1f OHCI GUIDLo[31:24] 0x20 OHCI ConfigRomHdr[7:0] 0x21 OHCI ConfigRomHdr[15:8] 0x22 OHCI ConfigRomHdr[23:16] 0x23 OHCI ConfigRomHdr[31:24] 0x24 Start of System Defined Configuration Space Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface Description FW323 05 137 ...
Page 138
... PCI PHY/Link Open Host Controller Interface Crystal Selection Considerations The FW323 is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to pro- vide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW323 have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used ...
Page 139
... TPA, TPB cable inputs, 200 Mbits/s operation TPA, TPB cable inputs, 400 Mbits/s operation 100 Mbits/s operation 200 Mbits/s operation 400 Mbits/s operation — — 200 Mbits/s 400 Mbits/s TPBIAS outputs At rated I/O current — FW323 05 Symbol Min Typ Max V 3.0 3.3 3.6 DD—SP V 142 — 260 ID— ...
Page 140
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Electrical Characteristics Table 123. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA+, TPA , TPB+, TPB Common-mode Speed Signaling Current, TPB+, TPB * Limits are defined as the algebraic sum of TPA+ and TPA driver currents. Limits also apply to TPB+ and TPB as the algebraic sum of driver currents. † ...
Page 141
... Data Out Setup Time for the FW323 SETUP_DATA t Rise Time for Serial Clock and Data Out from the FW323 RISE_TIME t Fall Time for Serial Clock and Data Out from the FW323 FALL_TIME t FW323 Setup Time for a Valid Stop Condition SETUP_STOP t Data Out Hold Time for EEPROM HOLD_EEPROM Agere Systems Inc ...
Page 142
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface ac Characteristics (continued) ROM_CLK t SETUP_START ROM_AD IN ROM_AD OUT ROM_CLK: serial clock, ROM_AD: serial data I/O ROM_CLK ROM_AD WORD n ROM_CLK: serial clock, ROM_AD: serial data I/O ROM_AD ROM_CLK ROM_CLK: serial clock, ROM_AD: serial data I/O 142 142 t t PW_LOW ...
Page 143
... ROM_CLK: serial clock, ROM_AD: serial data I/O ROM_CLK DATA IN DATA OUT ROM_CLK: serial clock Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface ROM_AD START Figure 8. Start and Stop Definition 1 START Figure 9. Output Acknowledge FW323 05 STOP 8 9 ACK 1311 (F) R.02 1312 (F) R.02 143 ...
Page 144
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Register Configuration PHY Core Register Map for Cable Environment The PHY core register map is shown below in Table 128. Table 128. PHY Core Register Map for the Cable Environment Address Bit 0 Bit 1 0000 ...
Page 145
... Powerup reset value is set by CONTENDER pin. 000 The difference between the fastest and slowest repeater data delay, expressed as (jitter + ns. self-ID packet. See Section 4.3.4.1 of IEEE Standard 1394-1995 for the encoding of this field. PC0, PC1, and PC2 pins set up power reset value. FW323 05 Description 145 ...
Page 146
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Register Configuration Table 129. PHY Core Register Fields for Cable Environment (continued) Field Size Type Power Reset Value Watchdog 1 RW ISBR 1 RW Loop 1 RW Pwr_fail 1 RW Timeout 1 RW Port_event 1 RW Enab_accel 1 RW ...
Page 147
... XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX 1111 2 REQUIRED Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface (continued) Contents Bit 2 Bit 3 Bit 4 BStat Child Connected XXXXX XXXXX XXXXX Int_enable Fault XXXXX RESERVED FW323 05 Bit 5 Bit 6 Bit 7 Bias Disabled 147 ...
Page 148
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Internal Register Configuration The meaning of the register fields with the port status page are defined by Table 131 below. Table 131. PHY Core Register Port Status Page Fields Field Size Type AStat 2 R BStat ...
Page 149
... Field Size Type Compliance_level 8 r Vendor_ID 24 r Product_ID 24 r Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW323. Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface (continued) Contents Bit 2 Bit 3 Bit 4 Compliance_level Vendor_ID Product_ID XXXXX ...
Page 150
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Outline Diagrams 128-Pin TQFP Dimensions are in millimeters. 16.00 0.20 14.00 0.20 PIN #1 IDENTIFIER ZONE 128 DETAIL A 0.50 TYP 150 103 102 20.00 0.20 22.00 0. DETAIL B 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.05/0.15 Data Sheet, Rev. 2 October 2001 1.00 REF 0.25 GAGE PLANE SEATING PLANE 0.45/0.75 DETAIL A ...
Page 151
... Data Sheet, Rev. 2 October 2001 Notes Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Interface FW323 05 151 ...
Page 152
... FW323 05 1394A PCI PHY/Link Open Host Controller Interface Microsoft and Windows are registered trademarks of Microsoft Corporation. MacOS is a registered trademark of Apple Computer, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www ...