M5M54R08J-15 MITSUBISHI, M5M54R08J-15 Datasheet

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M5M54R08J-15

Manufacturer Part Number
M5M54R08J-15
Description
4194304-bit (524288-word by 8-bit) CMOS static RAM
Manufacturer
MITSUBISHI
Datasheet
• Fast access time
• Low power dissipation
• Single +5V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
DESCRIPTION
The M5M54R08J is a family of 524288-word by 8-bit static
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
lead package(SOJ).
TTL compatible. They include a power down feature as well.
FEATURES
APPLICATION
High-speed memory units
The M5M54R08J is offered in a 36-pin plastic small outline J-
These device operate on a single 5V supply, and are directly
address
inputs
BLOCK DIAGRAM
OE 31
W
S
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
14
15
16
17
13
1
2
3
4
5
6
M5M54R08J-15
M5M54R08J-12
Active
Stand by
••••••••••
••••••••••
••••
••••
18
12ns(max)
550mW(typ)
A
15ns(max)
address
9
COLUMN INPUT BUFFERS
A
5mW(typ)
COLUMN I/O CIRCUITS
20 21 22 23 24
10
COLUMN ADDRESS
COLUMN
ADDRESS
MEMORY ARRAY
A
8192 COLUMNS
11
DECODERS
DECODERS
512 ROWS
A
12
MITSUBISHI
ELECTRIC
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
A
13
A
inputs
PACKAGE
14
data inputs/
outputs
36pin 400mil SOJ
PIN CONFIGURATION (TOP VIEW)
chip select
write control
input
input
address
data
inputs/
outputs
inputs
A
address
inputs
32 33
15
A
(5V)
(0V)
16
34 35
A
16
V
GND
A
DQ
DQ
DQ
DQ
CC
17
A
W
A
A
A
A
S
A
A
A
A
A
4
0
1
2
3
5
6
7
8
9
1
2
3
4
Outline
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
M5M54R08J-12,-15
36P0K (SOJ)
MITSUBISHI LSIs
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OE
GND
NC
DQ
V
DQ
DQ
A
A
A
A
A
NC
1997.11.20 Rev.F
DQ
A
A
A
A
CC
14
13
12
11
10
18
17
16
15
11
12
25
26
29
30
10
8
27
28
7
9
6
5
8
7
output enable
input
(0V)
(5V)
VCC
DQ
GND
address
DQ
DQ
DQ
DQ
address
DQ
DQ
DQ
inputs
data
inputs/
outputs
inputs
data
inputs/
outputs
3
1
2
4
5
6
7
8
data
inputs/
outputs
(5V)
(0V)
1

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M5M54R08J-15 Summary of contents

Page 1

... These device operate on a single 5V supply, and are directly TTL compatible. They include a power down feature as well. FEATURES • Fast access time M5M54R08J-12 M5M54R08J-15 • Low power dissipation Active Stand by • Single +5V power supply • Fully static operation : No clocks, No refresh • ...

Page 2

... FUNCTION The operation mode of the M5M54R08J is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. ...

Page 3

... V =1. •••••••••• V =1.5V, V =1. Fig1 ,Fig2 DQ Fig.2 Output load for MITSUBISHI ELECTRIC MITSUBISHI LSIs M5M54R08J-12,-15 Limit Unit Typ Min Max 7 8 Vcc 480 5pF (including 255 scope and JIG) en dis ...

Page 4

... MITSUBISHI ELECTRIC MITSUBISHI LSIs M5M54R08J-12,-15 Limits M5M54R08J -12 M5M54R08J -15 Max Min Min Limits M5M54R08J -12 M5M54R08J -15 Min Max Min ...

Page 5

... Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (A) tv (A) UNKNOWN (S) (Note 5) ten (S) UNKNOWN (OE) (Note 5) ten (OE) UNKNOWN MITSUBISHI ELECTRIC MITSUBISHI LSIs M5M54R08J-12,-15 tv (A) DATA VALID (Note 5) t dis (S) DATA VALID t PD 50% (Note 5) t dis (OE) DATA VALID 5 ...

Page 6

... DATA STABLE (Note 5) t dis (W) t dis (OE) Hi tsu (S) tsu ( ( (Note7) tsu (D) IH DATA STABLE IL t dis (W) ten (S) (Note5) OH (Note5) Hi-Z OL (Note8) MITSUBISHI ELECTRIC MITSUBISHI LSIs M5M54R08J-12,-15 (Note7) ten (Note 5) (OE) ten (W) trec (W) (Note7) th (D) 6 ...

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