M5M51016BTP-70LL MITSUBISHI, M5M51016BTP-70LL Datasheet

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M5M51016BTP-70LL

Manufacturer Part Number
M5M51016BTP-70LL
Description
1048576-bit (65536-word by 16-bit) CMOS static RAM
Manufacturer
MITSUBISHI
Datasheet

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DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM
organized as 65536 word by 16-bit which are fabricated using high-
performance triple polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery result in a high
density and low power static RAM.
for the battery back-up application.
outline package which is a high reliability and high density surface
mount device (SMD). Two types of devices are available. M5M510
16BTP(normal lead bend type package), M5M51016BRT (reverse
lead bend type package). Using both types of devices, it becomes
very easy to design a printed circuit board.
FEATURES
APPLICATION
Small capacity memory units
The M5M51016BTP,RT are packaged in a 44-pin thin small
They are low stand-by current and low operation current and ideal
M5M51016BTP,RT-70L
M5M51016BTP,RT-10L
M5M51016BTP,RT-70LL
M5M51016BTP,RT-10LL
Single +5.0V power supply
Low stand-by current 0.3 A (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by CS, BC
Data hold on +2V power supply
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51016BTP,RT
Type name
..............................
Access time
100ns
(max)
100ns
70ns
70ns
Power supply current
Active
(1MHz)
(max)
30mA
44pin 400mil TSOP(II)
(V
(V
(V
typ)
1
stand-by
CC
CC
CC
20 A
0.3 A
100 A
& BC
(max)
= 5.5V)
= 5.5V)
= 3.0V,
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI
ELECTRIC
2
PIN CONFIGURATION (TOP VIEW)
OUTPUT ENABLE
CHIP SELECT
M5M51016BTP,RT-70L,-10L,
M5M51016BTP,RT-70L,-10L,
OUTPUTS
CONTROL
CONTROL
ADDRESS
ADDRESS
ADDRESS
OUTPUTS
INPUTS/
INPUTS
INPUTS
INPUTS/
INPUTS
INPUTS
INPUTS
Outline 44P3W - H (400mil TSOP Normal Bend)
Outline 44P3W - J (400mil TSOP Reverse Bend)
WRITE
DATA
BYTE
DATA
INPUT
INPUT
(0V)GND
(0V)GND
(5V)V
DQ
NC
BC
BC
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
W
A
NC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
A
A
A
A
CS
OE
14
15
13
9
11
10
8
NC
12
7
6
5
4
3
2
1
0
CC
1
2
14
16
15
13
12
11
10
9
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
-70LL,-10LL
-70LL,-10LL
MITSUBISHI LSIs
MITSUBISHI LSIs
10
11
12
13
14
15
16
17
18
19
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
20
21
22
1
2
3
4
5
6
7
8
9
NC : NO CONNECTION
GND(0V)
NC
BC
BC
NC
A
A
A
W
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
NC
A
A
A
A
A
A
A
A
A
CS
GND(0V)
NC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE
14
15
13
8
9
11
10
CC
12
7
6
5
4
3
2
1
0
1
2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(5V)
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
9 Jul ,1997
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
WRITE
CONTROL
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
INPUTS
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
9 Jul ,1997
1

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M5M51016BTP-70LL Summary of contents

Page 1

... DESCRIPTION The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high- performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low stand-by current and low operation current and ideal for the battery back-up application ...

Page 2

... BC2 WRITE CONTROL W 38 INPUT OUTPUT ENABLE OE 13 INPUT M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM When setting BC the chips are in a non-selectable mode in which both reading and , BC , CS, W and 1 2 writing are disabled. In this mode, the output stage high-impedance state, ...

Page 3

... C I Input capacitance ( BC , IBC C Output capacitance O Note 1: Direction for current flowing into positive (no mark Typical value is Vcc = 5.0V M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM Conditions With respect to GND Ta= (Ta=0 ~ Vcc=5. unless otherwise noted) C Test conditions I = – ...

Page 4

... Write recovery time rec(W) t Output disable time from W low dis(W) t Output disable time from OE high dis(OE) t en(W) Output enable time from W high t en(OE) Output enable time from OE low M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM + unless otherwise noted ) 0. 1.5V OL ...

Page 5

... W = "H" level Write cycle (W control mode and/ (Note 3) CS (Note M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM a( (BC1 (BC2 (CS (OE (OE (BC1 (BC2 (CS) ...

Page 6

... Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while CS high overlaps BC 5: When the falling edge simultaneously or prior to the falling edge of BC maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode. M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM ...

Page 7

... Power down set up time su (PD) t Power down recovery time rec (PD) (3) POWER DOWN CHARACTERISTICS BC control mode V CC 2.2V BC & control mode 0.2V M5M51016BTP,RT-70L,-10L, 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM o ( unless otherwise noted) Test conditions < 2.2V V CC(PD) 2 < < 2.0V V 2.2V CC(PD) < ...

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