93C66 Fairchild Semiconductor, 93C66 Datasheet
93C66
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93C66 Summary of contents
Page 1
... Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of FM93C66A offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space consid- erations ...
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... Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the FM93C66A Rev. B ...
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... CSH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP FM93C66A Rev. B.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C66A +6.5V to -0.3V FM93C66AE FM93C66AV +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...
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... KHz (Note 6) C Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) FM93C66A Rev. B.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C66AL/LZ +6.5V to -0.3V FM93C66ALE/LZE FM93C66ALV/LZV +300°C Power Supply ( 2000V V = 2.7V to 4.5V unless otherwise specified. Refer ...
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... This is an active high input pin to FM93C66A EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently ...
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... Opcode and Address) for this WEN instruction should be issued as listed under Table 1 or Table 2. The device becomes write- enabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WEN instruc- tion. Refer Write Enable cycle diagram. FM93C66A Rev. B.1 Opcode Field Address Field 10 A8 ...
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... Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table FM93C66A Rev. B.1 2. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle ...
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... DI Start Bit DO A =A7 93C66A (ORG=1; n Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don’t Care, can 93C66A (ORG=0; A =A8 n Address bits pattern -> 1-1-x-x-x-x-x-x-x; (x -> Don’t Care, can FM93C66A Rev. B SKH SKL t DIH Valid Input Valid ...
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... Sta =A7; D 93C66 -> -x-x-x-x-x-x; (x -> D on't Care, can =A8; D 93C66 > -x-x-x-x-x-x-x; (x -> Don't C are FM93C66A Rev ...
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... FM93C66A Rev. B ...
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... All lead tips Typ. All Leads FM93C66A Rev. B.1 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ ...
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... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 FM93C66A Rev. B.1 5 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation 4 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0118 (0.19 - 0.30) 0¡-8¡ DETAIL A Typ. Scale: 40X ...
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... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. FM93C66A Rev. B.1 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...