AD9572 Analog Devices, AD9572 Datasheet
AD9572
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AD9572 Summary of contents
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... No external loop filter components are required, thus conserving valuable design time and board space. The AD9572 is available in a 40-lead × lead frame chip scale package (LFCSP) and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C. ...
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... AD9572 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 PLL Characteristics ...................................................................... 3 LVDS Clock Output Jitter ............................................................ 4 LVPECL Clock Output Jitter ....................................................... 5 CMOS Clock Output Jitter .......................................................... 5 Reference Input ............................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 6 Control Pins .................................................................................. 7 Power .............................................................................................. 7 Crystal Oscillator .......................................................................... 7 Timing Diagrams .............................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...
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... MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled dBc/Hz 33.33 MHz output disabled AD9572 ...
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... AD9572 Parameter PLL Noise (125 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (100 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Phase Noise (33.33 MHz CMOS Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 5 MHz Phase Noise (25 MHz CMOS Output) ...
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... Minimum (min) and maximum (max) values are given A Min Typ Max 25 2.0 0.8 −1.0 +1.0 2 Rev Page AD9572 Unit Test Conditions/Comments f rms LVPECL output frequency combinations S are 1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz f rms LVPECL output frequency combinations S are 1 × ...
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... AD9572 CLOCK OUTPUTS Typical (typ) is given for V = 3.3 V ± 10 over full V and T (−40°C to +85°C) variation Table 6. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage ( Output Low Voltage ( Output Differential Voltage ( Duty Cycle LVDS CLOCK OUTPUTS ...
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... Test Conditions/Comments REFSEL has a 30 kΩ pull-up resistor. FREQSEL has a 150 kΩ pull-up resistor and a 100 kΩ pull-down resistor. FORCE_LOW has a 16 kΩ pull-down resistor. Unit Test Conditions/Comments Unit Test Conditions/Comments Fundamental mode MHz Ω pF dBc/ kHz offset ppm AD9572 ...
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... AD9572 TIMING DIAGRAMS DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential Rev Page SINGLE-ENDED 80% CMOS 5pF LOAD 20 Figure 5. CMOS Timing, Single-Ended Load ...
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... JA soldered in a circuit board for surface-mount packages. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. Table 12. Thermal Resistance Package Type 40-Lead LFCSP ESD CAUTION Rev Page AD9572 θ Unit JA 27.5 °C/W ...
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... VS 27 FREQSEL 28 VS 29, 31 106M 30, 32 106M GND 1 PIN 1 30 106M INDICATOR 106M FREQSEL 25M 4 AD9572 TOP VIEW (Not to Scale REFCLK 8 23 33M REFSEL 9 22 100M/125M 21 100M/125M GND 10 Figure 6. Pin Configuration Description No Connect ...
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... Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers. Power Supply Connection for the FC VCO. Forces the 33.33 MHz output into a low state. Power Supply Connection for the FC PLL. Power Supply Connection for Miscellaneous Logic. Rev Page AD9572 ...
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... AD9572 TYPICAL PERFORMANCE CHARACTERISTICS Both 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled. –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. 106.25 MHz Phase Noise –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 8. 125 MHz Phase Noise – ...
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... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9572 ...
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... DETECTOR FREQUENCY DETECTOR AD9572 Figure 12 shows a block diagram of the AD9572. The chip combines dual PLL cores, which are configured to generate the specific clock frequencies required for networking applications, without any user programming. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance ...
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... POWER SUPPLY The AD9572 requires a 3.3 V ± 10% power supply for V tables in the Specifications section give the performance expected from the AD9572 with the power supply voltage within this OUT range. The absolute maximum range of −0 +3.6 V, with OUTB respect to GND, must never be exceeded on the VS pin ...
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... Figure 16. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9572 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 17. The far-end termination network should match the PCB trace impedance and provide the desired switching point ...
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... AD9572ACPZPEC −40°C to +85° AD9572ACPZPEC-RL −40°C to +85°C AD9572ACPZPEC- −40°C to +85° AD9572-EVALZ-LVD AD9572-EVALZ-PEC RoHS Compliant Part. 2 LVD indicates LVDS compliant, differential clock outputs. 3 PEC indicates LVPECL compliant, differential clock outputs. 6.10 0.30 6 ...
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... AD9572 NOTES Rev Page ...
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... NOTES Rev Page AD9572 ...
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... AD9572 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07498-0-7/09(0) Rev Page ...