M4LV-128/64-7VC Lattice Semiconductor Corp., M4LV-128/64-7VC Datasheet

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FEATURES 2 ◆ High-performance, E CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs TM — Excellent First-Time-Fit TM — SpeedLocking performance for guaranteed fixed timing — Central, input and output switch matrices for 100% routability ...

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... COS t (ns) 5.5 SS Static Power (mA) 25 JTAG Compliant Yes PCI Compliant Yes Notes: 1. For information on the M4-96/96 device, please refer to the M4-96/96 data sheet at www.latticesemi.com. 2. “M4-xxx” is for 5-V devices. “M4LV-xxx” is for 3.3-V devices. 2 Table 1. MACH 4 Device Features M4-64/32 M4-96/48 M4-128/64 M4LV-64/32 M4LV-96/48 M4LV-128/ 128 32 ...

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... The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation. MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface ...

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... Table 3. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table) M4-32/32 M4-64/32 Package M4LV-32/32 M4LV-64/32 44-pin PLCC 32+2 44-pin TQFP 32+2 48-pin TQFP 32+2 84-pin PLCC 100-pin TQFP 100-pin PQFP 144-pin TQFP 208-pin PQFP 256-ball BGA 4 M4-96/48 M4-128/64 M4LV-96/48 M4LV-128/64 32+2 32+2 32+2 48+8 64+6 64+6 MACH 4 Family M4-128N/64 M4-192/96 M4LV-128N/64 M4LV-192/96 M4LV-256/128 64+6 96+16 128+14 128+14 ...

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FUNCTIONAL DESCRIPTION The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, ...

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... Product-term array ◆ Logic allocator ◆ Macrocells ◆ Output switch matrix ◆ I/O cells ◆ Input switch matrix ◆ Clock generator 6 MACH 4 Devices M4-64/32, M4LV-64/32 M4-96/48, M4LV-96/48 M4-128/64, M4LV-128/64 M4-128N/64, M4LV-128N/64 M4-192/96, M4LV-192/96 M4-256/128, M4LV-256/128 2:1 Yes Yes Yes Yes MACH 4 Family M4-32/32 M4LV-32/32 1:1 Yes No Yes Yes ...

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... M4-64/32 and M4LV-64/32 M4-96/48 and M4LV-96/48 M4-128/64 and M4LV-128/64 M4-128N/64 and M4LV-128N/64 M4-192/96 and M4LV-192/96 M4-256/128 and M4LV-256/128 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fi ...

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Table 6. Logic Allocator for All MACH 4 Devices (except M4(LV)-32/32) Output Macrocell Output Macrocell ...

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Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 4. Logic Allocator Configurations: ...

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Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset ...

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The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that ...

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Configuration D-type Register T-type Register D-type Latch Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, ...

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A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. ...

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Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In MACH ...

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Table 10. Output Switch Matrix Combinations for MACH 4 Devices with 2:1 Macrocell M0, M1 M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13 M14, M15 I/O Cell I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Table ...

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I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except MACH 4 devices with 1:1 macrocell-I/O cell ratio.) An individual output enable product term is provided for each ...

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Figure 12. MACH 4 with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix PAL Block Clock Generation Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a clock generator in each ...

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Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 Note: 1. Values in parentheses are for the M4(LV)-32/32 and M4(LV)-64/32. This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven ...

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MACH 4 TIMING MODEL The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH 4 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and ...

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IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a ...

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POWER MANAGEMENT Each individual PAL block in MACH 4 devices features a programmable low-power mode, which results in power savings 50%. The signal speed paths in the low-power PAL block will be slower than those in the ...

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INPUT SWITCH MATRIX Figure 16. PAL Block for MACH 4 with 2:1 Macrocell - I/O Cell Ratio 22 M4(LV)-64/32, M4(LV)-96/48, M4(LV)-128/64 CLOCK A 16 GENERATOR MACROCELL ...

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INPUT 32 SWITCH MATRIX Figure 17. PAL Block for M4(LV)-32/32 CLK0/I0 CLK0/I1 CLOCK GENERATOR MACROCELL MACROCELL MACROCELL MACROCELL ...

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BLOCK DIAGRAM – M4(LV)-32/ Block A I/O8–I/O15 8 I/O Cells 8 Output Switch 8 Matrix Macrocells AND Logic Array and Logic Allocator 16 33 Central Switch Matrix ...

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BLOCK DIAGRAM – M4(LV)-64/ Block A I/O0–I/O7 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array AND ...

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BLOCK DIAGRAM – M4(LV)-96/48 Clock Generator Clock Generator Clock Generator 26 I2, I3, I6, I7 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 ...

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BLOCK DIAGRAM – M4(LV)-128N/64 AND M4(LV)-128/64 Clock Generator Clock Generator Clock Generator Clock Generator I2, I5 Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE ...

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BLOCK DIAGRAM – M4(LV)-192/96 Block B I/O8–I/O15 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator 24 34 Block C I/O16–I/O23 Block D I/O24–I/O31 ...

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BLOCK DIAGRAM – M4(LV)-256/128 Block B I/O8–I/O15 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator AND ...

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ABSOLUTE MAXIMUM RATINGS M4 Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . ...

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... ABSOLUTE MAXIMUM RATINGS M4LV Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55°C to +100°C Device Junction Temperature . . . . . . . . . . . . . +130°C Supply Voltage with Respect to Ground . . . . . . . . . . . -0 +4 Input Voltage . . . . . . . . . . . . . . . . . -0 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (T = -40°C to +85°C 200 mA ...

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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: t Internal combinatorial propagation delay PDi t Combinatorial propagation delay PD Registered Delays: t Synchronous clock setup time, D-type register SS t Synchronous clock setup time, T-type register SST t Asynchronous ...

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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Input Latch Delays with ZHT Option: t Input latch setup time - ZHT SILZ t Input latch hold time - ZHT HILZ t Transparent input latch to internal feedback - ZHT PDILZi Output ...

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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Frequency: External feedback, D-type, Min of 1/(t WLS 1/( COS External feedback, T-type, Min of 1/(t WLS 1/( SST COS Internal feedback (f ), D-type, CNT ...

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I vs. FREQUENCY CC These curves represent the typical power consumption for a particular device at system frequen- cy. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown ...

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PLCC CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View M4(LV)-64 I/O7 TDI CLK0/I0 M4(LV)-32/32 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4(LV)-64/32 PIN DESIGNATIONS CLK/I ...

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TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View M4(LV)-64 I/O7 TDI M4(LV)-32/32 CLK0/I0 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4(LV)-64/32 PIN DESIGNATIONS CLK/I ...

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TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32) Top View M4(LV)-64 I/O7 TDI CLK0/I0 M4(LV)-32/32 NC GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4(LV)-64/32 PIN DESIGNATIONS ...

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TQFP CONNECTION DIAGRAM (M4(LV)-96/48) Top View NC 1 TDI I/O10 9 B3 I/O11 10 I0/CLK0 GND 13 ...

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PLCC CONNECTION DIAGRAM (M4(LV)-128N/64) Top View I/ I/ I/O10 B4 I/O11 15 B3 I/O12 I/O13 B1 I/O14 18 B0 I/O15 19 20 CLK ...

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PQFP CONNECTION DIAGRAM (M4(LV)-128/64) Top View GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 ...

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TQFP CONNECTION DIAGRAM (M4(LV)-128/64) Top View GND 1 TDI I/O10 5 B4 I/O11 6 B3 I/O12 7 B2 I/O13 8 B1 I/O14 9 B0 I/O15 10 I0/CLK0 ...

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TQFP CONNECTION DIAGRAM (M4(LV)-192/96) Top View GND 1 TDI ...

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PQFP CONNECTION DIAGRAM (M4(LV)-256/128) Top View GND 1 TDI 2 C7 I/O16 3 C6 I/O17 4 C5 I/O18 5 C4 I/O19 6 C3 I/O20 7 C2 I/O21 8 C1 I/O22 9 C0 I/O23 10 VCC 11 GND 12 D7 ...

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... BGA CONNECTION DIAGRAM (M4LV-256/128) Bottom View I/O108 I/O105 A GND N/C GND GND N4 N1 I/O113 I/O109 I/O106 I/O103 B GND N I/O116 I/O111 I/O107 C N/C VCC TRST I/O120 I/O117 I/O112 I/O110 D VCC VCC I/O123 I/O119 I/O114 E TDI ...

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... Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Com- bination) is formed by a combination of: FAMILY TYPE M4- = MACH 4 Family (5 M4LV- = MACH 4 Family Low Voltage (3.3-V V MACROCELL DENSITY Macrocells 128N = 128 Macrocells, Non-ISP Macrocells 192 = 192 Macrocells ...