MC68HC805PV8YDW Freescale Semiconductor, Inc, MC68HC805PV8YDW Datasheet
MC68HC805PV8YDW
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MC68HC805PV8YDW Summary of contents
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... MC68HC05PV8/D REV 1.9 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MC68HC05PV8 MC68HC805PV8 MC68HC05PV8A Technical Data HCMOS Microcontroller Unit ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MC68HC05PV8 MC68HC805PV8 MC68HC05PV8A Technical Data — Rev 1.9 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A Contents Introduction Changes from Rev 1.5 published on September 9th, 1999 to Rev 1.6 published on May 4th, 2000 Changes from Rev 1.6 published on May 4th, 2000 to Rev 1.7 pub- lished on December 1st, 2000 Changes from Rev 1.7 published on December 1st, 2000 to Rev 1.8 published on February 20th, 2001 Changes from Rev 1 ...
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... Freescale Semiconductor, Inc. Technical Data Changes from Rev 1.5 published on September 9th, 1999 to Rev 1.6 published on May 4th, 2000 Section Page (in Rev 1.6) Changes from Rev 1.6 published on May 4th, 2000 to Rev 1.7 published on December 1st, 2000 Section Page (in Rev 1. Changes from Rev 1.7 published on December 1st, 2000 to Rev 1.8 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPU and Instruction Set Interrupts Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . 123 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 137 Pulse Width Modulator ...
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... Freescale Semiconductor, Inc. Technical Data EEPROM 157 Program EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Fast Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 173 Technical Data For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.8 2.1 2.2 2.3 2.4 2.5 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 VSUP, VSS and PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDD OSC1, OSC2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PA0– ...
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... Freescale Semiconductor, Inc. Technical Data 2.6 2.7 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 Technical Data For More Information On This Product, Program EEPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Section 3. CPU and Instruction Set Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Program Counter Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Arithmetic/Logic Unit (ALU .47 Instruction Set Overview .48 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Inherent ...
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... Freescale Semiconductor, Inc. 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.8.1 4.9 4.10 4.10.1 4.10.2 4.10.3 4.11 4.12 4.13 5.1 5.2 5.3 5.4 5.5 5.6 5.7 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 4. Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reset Interrupt Sequence Software Interrupt (SWI .70 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 External Interrupt (IRQ 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ambient Exception Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 High Temperature Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .73 High Voltage Interrupt ...
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... Freescale Semiconductor, Inc. Technical Data 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.14.1 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.1.1 6.5.2 6.6 Technical Data For More Information On This Product, Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 83 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . 83 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Disabled STOP Instruction Reset . . . . . . . . . . . . . . . . . . . . . . .84 High Temperature Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 High Voltage Reset Low Voltage Reset ...
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... Freescale Semiconductor, Inc. 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 7. Input/Output Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General Input/Output Programming . . . . . . . . . . . . . . . . . . . . . 94 Port Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port A Pull-up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Port A Voltage Reference for A/D Converter Port A Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 97 Port A Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . 98 Operational Amplifier .98 Port B ...
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... Freescale Semiconductor, Inc. Technical Data 8.4 8.5 9.1 9.2 9.3 9.3.1 9.3.2 9.3.2.1 9.3.2.2 9.3.3 9.3.3.1 9.3.3.2 9.3.4 9.3.5 9.3.6 9.4 9.5 10.1 10.2 10.3 10.4 10.5 10.6 10.6.1 10.6.2 10.7 10.8 Technical Data For More Information On This Product, Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Core Timer During STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Section 9. 16-Bit Programmable Timer Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Registers 126 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 127 Output Compare Register .127 Output Compare Register 2 ...
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... Freescale Semiconductor, Inc. 10.9 10.10 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 10.10.2 10.10.3 10.10.4 10.10.5 10.10.6 10.10.7 10.10.8 11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.5 11.6 11.7 11.8 12.1 12.2 12.3 12.4 12.5 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Transfer Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Gain Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Differential Linearity Error . . . . . . . . . . . . . . . . . . . . . . . . . 146 Integral Linearity Error 146 Total Unadjusted Error ...
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... Freescale Semiconductor, Inc. Technical Data 13.1 13.2 13.3 13.4 13.5 13.5.1 13.5.2 13.5.3 13.6 14.1 14.2 14.3 14.4 14.5 15.1 15.2 15.3 15.3.1 16.1 16.2 16.3 Technical Data For More Information On This Product, Section 13. EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EEPROM Control Register (EEPCR 158 EEPROM Options Register (EEOPR 159 EEPROM READ, ERASE and Programming Procedures . . . 160 READ Procedure 160 ERASE Procedure 160 Programming Procedure ...
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... Freescale Semiconductor, Inc. 16.4 16.5 16.6 16.7 16.8 16.9 16.9.1 16.10 Down Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 Die Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 Fast Peripheral Interface Timing 188 16.15 PORT C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 16.15.2 16.15.3 16.15.4 16.15.5 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Program and Data EEPROM Characteristics . . . . . . . . . . . . . 175 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 V Referenced Pins Electrical Characteristics ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Table of Contents Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 6-1 6-2 7-1 7-2 7-3 7-4 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Title MC68HC(8)05PV8/A Block Diagram . . . . . . . . . . . . . . . . . . 28 MC68HC(8)05PV8/A Pin Assignments . . . . . . . . . . . . . . . . 29 28-pin SOIC mechanical dimensions . . . . . . . . . . . . . . . . . . 30 MC68HC(8)05PV8/A Memory Map . . . . . . . . . . . . . . . . . . . 36 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I/O Registers $0000–$000F . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O Registers $0010– ...
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... Freescale Semiconductor, Inc. Technical Data 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 8-1 8-2 8-3 9-1 9-2 9-3 9-4 10-1 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 12-1 13-1 Technical Data For More Information On This Product, Typical application: positive Vgain amplifier Mapping Ports to Timer Capture Channels . . . . . . . . . . . .100 I/O Configuration Register (IOCFG 101 PC0 Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . . . 103 PC1–3 Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . 104 PC4 Contact Sense Circuitry 68HC(8)05PV8 . . . . . . . . . . 104 PC4 Circuitry 68HC05PV8A ...
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... Freescale Semiconductor, Inc. 13-2 14-1 14-2 15-1 15-2 16-1 16-2 16-3 16-4 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, EEPROM Options Register (EEOPR 159 Program EEPROM Control Register (PEECR 164 Options Register 166 Basic Fast Peripheral Interface Timing . . . . . . . . . . . . . . . 170 System Control Register (SYSCR 171 Low Voltage Reset waveform 181 VSUP related Reset and Interrupts waveforms ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, List of Figures Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A Table 1-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 6-1 7-1 7-2 7-3 8-1 8-2 10-2 10-1 11-1 11-2 11-3 12-1 13-1 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Title Ordering Information Register/Memory Instructions Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 53 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 55 Bit Manipulation Instructions Control Instructions Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 67 IRQ sensitivity ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, List of Tables Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 1.1 Contents 1.2 1.3 1.4 1.5 1.5 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.8 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 VSUP, VSS and PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDD OSC1, OSC2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PA0– ...
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... Freescale Semiconductor, Inc. Technical Data 1.2 Introduction The MC68HC05PV8, MC68HC805PV8 and MC68HC05PV8A microcontrollers are members of Motorola’s 68HC05 family, designed for low-cost and single-chip systems in automotive applications. They combine an HC05 core with a shell of high-voltage peripherals. Throughout this book, the term MC68HC(8)05PV8/A is used to refer to all three MCUs ...
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... Freescale Semiconductor, Inc. • • • • • • • • • • • • • • • • MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, On-Chip 5V ( 5%) Voltage Regulator including Power-On Reset, with 20mA supply for External Devices. VSUP Range 16V. ...
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... Freescale Semiconductor, Inc. Technical Data PROGRAM EEPROM/USER ROM — 8K USER VECTORS —16 BYTES MONITOR ROM — 240 BYTES EEPROM — 128BYTES USER RAM — 192BYTES CPU CONTROL IRQ M68HC05 MCU RESET RESET STACK POINTER PROGRAM COUNTER ...
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... Freescale Semiconductor, Inc. 1.4 Mask Options There are five mask options on the MC68HC(8)05PV8/A: • • • • • 1.5 Pin Assignments Figure 1-2 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, STOP Instruction (enable/disable) COP Watchdog Timer (enable/disable) Clock Monitor (enable/disable) High Temperature Reset (enable/disable) High Voltage Reset (enable/disable) shows the 28-pin SOIC pin assignments ...
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... Freescale Semiconductor, Inc. Technical Data 1.6 Mechanical Specifications 1 G Dim Technical Data For More Information On This Product, – A – – B – Case 751F- 0.25 T Min. Max. Notes 17.80 18.05 7.40 7.60 1. Dimensions ‘A’ and ‘B’ are datums and ‘T’ datum surface. ...
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... Freescale Semiconductor, Inc. 1.7 Functional Pin Descriptions The following paragraphs give a description of the general function for each pin. 1.7.1 VSUP, VSS and PVSS The microcontroller is operated from a single power supply. VSUP is connected to the positive supply, VSS to ground. The on-chip voltage regulator uses VSUP to derive the VDD supply for the MCU and external components ...
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... Freescale Semiconductor, Inc. Technical Data 1.7.5 IRQ The interrupt triggering sensitivity of this pin can be programmed as rising/falling edge sensitive or high/low level sensitive.The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See 1.7.6 PA0–PA7/VREFH, VREFL, AN1–6, IN, IIN, OUT These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset ...
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... Section 9. 16-Bit for more details on the operation of the 16-Bit for more details on the I/O ports. Table 1-1 Ordering Information Temperature Package Type range (JUNCTION) 28-pin SOIC – +125 C General Description Go to: www.freescale.com General Description Ordering Information (1) Order Number MC68HC05PV8YDW MC68HC805PV8YDW MC68HC05PV8AYDW Technical Data ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, General Description Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Registers RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program EEPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Memory Go to: www.freescale.com Section 2. Memory Technical Data ...
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... Freescale Semiconductor, Inc. Technical Data 2.2 Introduction The MC68HC(8)05PV8/A has a 16K byte memory map consisting of registers (for I/O, control and status), user RAM, user ROM (or program EEPROM), EEPROM, Monitor ROM, and reset and interrupt vectors as shown in Technical Data For More Information On This Product, Figure 2-1 ...
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... Freescale Semiconductor, Inc. 2.3 Registers The I/O and control registers reside in locations $0000–$002F. The overall organization of these registers is shown in assignments for each register are shown in Figure MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, 2-4. Addr Register Name $0000 Port A data register ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Addr Register Name $001B Timer alternate counter low $001C Timer control 1 $001D Timer control 2 $001E Timer status $001F TEST $0020 Port A configuration register $0021 I/O configuration register $0022 Port C configuration register 0 ...
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... Freescale Semiconductor, Inc. Addr Register R/W R Port A Data $0000 W R $0001 Port B Data W R $0002 Port C Data W R $0003 Unused W R $0004 Port A Data Direction W R $0005 Port B Data Direction W R $0006 Port C Data Direction W R $0007 Unused W R $0008 CTSCR W R $0009 ...
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... Freescale Semiconductor, Inc. Technical Data Addr Register R/W R Timer Input Capture1 $0010 High W R Timer Input Capture1 $0011 Low W R Timer Output $0012 Compare1 High W R Timer Output $0013 Compare1 Low W R Timer Input Capture2 $0014 High W R Timer Input Capture2 $0015 ...
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... Freescale Semiconductor, Inc. Addr Register R/W R $0020 Port A Configuration W R $0021 I/O Configuration W R $0022 Port C Configuration $0023 Unused W R $0024 Port A Interrupt Status W R $0025 Unused W R $0026 Port C Configuration $0027 Port C Status W R Interrupt Control $0028 Register W R Interrupt Status ...
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... Freescale Semiconductor, Inc. Technical Data 2.4 RAM The user RAM consists of 192 bytes ranging from $0040 to $00FF. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. The stack is located in the RAM address space. Data written to addresses within the stack address range could be overwritten during stack activity ...
Page 43
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 3.1 Contents 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 3. CPU and Instruction Set CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Arithmetic/Logic Unit (ALU .47 Instruction Set Overview .48 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Indexed,16-Bit Offset ...
Page 44
... Freescale Semiconductor, Inc. Technical Data 3.2 CPU Registers Figure 3-1 the memory map PCH CARRY/BORROW FLAG 3.2.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. Bit 7 Reset: ...
Page 45
... Freescale Semiconductor, Inc. 3.2.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. Bit 7 Reset: The 8-bit index register can also serve as a temporary data storage location. 3.2.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack ...
Page 46
... Freescale Semiconductor, Inc. Technical Data 3.2.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...
Page 47
... Freescale Semiconductor, Inc. Interrupt Mask Setting the interrupt mask disables interrupts interrupt request occurs while the interrupt mask is logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector interrupt request occurs while the interrupt mask is set, the interrupt request is latched ...
Page 48
... Freescale Semiconductor, Inc. Technical Data operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. 3.4 Instruction Set Overview The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction ...
Page 49
... Freescale Semiconductor, Inc. increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 3.5.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte ...
Page 50
... Freescale Semiconductor, Inc. Technical Data 3.5.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. ...
Page 51
... Freescale Semiconductor, Inc. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 3.6 Instruction Types The MCU instructions fall into the following five categories: • ...
Page 52
... Freescale Semiconductor, Inc. Technical Data 3.6.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Technical Data For More Information On This Product, ...
Page 53
... Freescale Semiconductor, Inc. 3.6.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, ...
Page 54
... Freescale Semiconductor, Inc. Technical Data 3.6.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...
Page 55
... Freescale Semiconductor, Inc. MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Table 3-3 Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same ...
Page 56
... Freescale Semiconductor, Inc. Technical Data 3.6.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations ...
Page 57
... Freescale Semiconductor, Inc. 3.6.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Table 3-5 Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt ...
Page 58
... Freescale Semiconductor, Inc. Technical Data 3.7 Instruction Set Summary Table 3-6 Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ADD opr,X ADD opr,X ...
Page 59
... Freescale Semiconductor, Inc. Table 3-6 Instruction Set Summary (Continued) Source Operation Form BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X BLO rel ...
Page 60
... Freescale Semiconductor, Inc. Technical Data Table 3-6 Instruction Set Summary (Continued) Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX Complement Byte (One’ ...
Page 61
... Freescale Semiconductor, Inc. Table 3-6 Instruction Set Summary (Continued) Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr ...
Page 62
... Freescale Semiconductor, Inc. Technical Data Table 3-6 Instruction Set Summary (Continued) Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC #opr SBC opr ...
Page 63
... Freescale Semiconductor, Inc. Table 3-6 Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulatoropr C Carry/borrow flagPC CCRCondition code registerPCH ...
Page 64
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Instruction Set Summary CPU and Instruction Set Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 65
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.8.1 4.9 4.10 4.10.1 4.10.2 4.10.3 4.11 4.12 4.13 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reset Interrupt Sequence Software Interrupt (SWI .70 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 External Interrupt (IRQ 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ambient Exception Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 High Temperature Interrupt ...
Page 66
... Freescale Semiconductor, Inc. Technical Data 4.2 Introduction The MCU can be interrupted in different ways: 1. Nonmaskable Software Interrupt Instruction (SWI) 2. External Asynchronous Interrupt (IRQ) 3. External Asynchronous Interrupt on Port A 4. External Asynchronous Interrupt on Port C 5. Internal 8-bit Timer Interrupt (CTIMER) 6. Internal 16-bit Timer1 Interrupt (TIMER) 7. Low Voltage Interrupt 8. Port C5 & ...
Page 67
... Freescale Semiconductor, Inc. When an interrupt processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF0 through $3FFF as defined in Table 4-1 Reset/Interrupt Vector Addresses Function Power-On Logic RESET Pin COP Watchdog Low Voltage Reset ...
Page 68
... Freescale Semiconductor, Inc. Technical Data Table 4-1 Reset/Interrupt Vector Addresses Function Voltage, Temperature and Port C Short circuit Interrupts Port A High Nibble Interrupt Port A Low Nibble Interrupt Port C Contact Sense/HV Inputs The M68HC05 CPU does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead ...
Page 69
... Freescale Semiconductor, Inc. Y FETCH NEXT INSTRUCTION Y RESTORE REGISTERS FROM STACK: CCR,A,X,PC Figure 4-1 Interrupt Processing Flowchart MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, FROM RESET I-BIT IN CCR SET CLEAR IRQ REQUEST IRQ? LATCH N INTERNAL Y 8 BIT CORE TIMER INTERRUPT? ...
Page 70
... Freescale Semiconductor, Inc. Technical Data 4.4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however acted upon in a similar manner as shown in on the RESET pin or internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $3FFE and $3FFF ...
Page 71
... Freescale Semiconductor, Inc. the CPU is pushed onto the stack and the I-bit is set. This masks further interrupts until the present one is serviced. The interrupt service routine address is specified by the contents of memory locations $3FFA and $3FFB. $000A Read: Write: Reset: INTP, INTN – External interrupt sensitivity options ...
Page 72
... Freescale Semiconductor, Inc. Technical Data Table 4-1 pin, however it is important to re-emphasize here that in order to avoid any conflict and spurious interrupt only possible to change the external interrupt options while the I-bit is set. Any attempt to change the external interrupt option while the I-bit is clear will be unsuccessful external interrupt is pending, it will automatically be cleared when selecting a different interrupt option ...
Page 73
... Freescale Semiconductor, Inc. 4.9 Ambient Exception Interrupts There are three different interrupt flags that cause an environmental exception interrupt whenever they are set and enabled. The interrupt flags are in the reset/interrupt status register (INTSR), and the enable bits are in the interrupt control register (INTCR). Any of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory location $3FF4 and $3FF5 ...
Page 74
... Freescale Semiconductor, Inc. Technical Data HTIE – High Temperature Interrupt Enable This bit enables/disables the high temperature interrupt. Once this interrupt is acknowledged, the enable bit should be cleared and the high temperature interrupt flag should be monitored until the bit is cleared High temperature interrupt enabled 0 = High temperature interrupt disabled 4 ...
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... Freescale Semiconductor, Inc. LVIE – Low Voltage Interrupt Enable This bit enables/disables the low voltage interrupt. Once this interrupt is acknowledged, the enable bit should be cleared and the low voltage interrupt flag should be monitored until the bit is cleared Low voltage interrupt enabled 0 = Low voltage interrupt disabled 4 ...
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... Freescale Semiconductor, Inc. Technical Data as an output, the signal for the corresponding CSDx bit, and therefore for the contact sense interrupt, is derived from the high-voltage input circuit. For details see 4.13 STOP and WAIT Modes All modules that are capable of generating interrupts in STOP or WAIT mode can only do so when configured properly ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.14.1 5.2 Introduction The MCU can be reset from nine sources: one external input and eight internal restart conditions. The RESET pin is an input with a Schmitt trigger. All the internal peripheral modules are reset by the internal reset signal (RST). Refer to MC68HC(8)05PV8/A — ...
Page 78
... Freescale Semiconductor, Inc. Technical Data 5.3 Reset status register (RSR) This register contains eight flags that show the source of the last reset. A power-on reset sets the POR bit in the system control register and clears all other bits in the reset status register. All bits can be cleared by writing a one to the corresponding bit ...
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... Freescale Semiconductor, Inc. HTR – High Temperature Reset Bit 1 = Last reset caused by high temperature detect circuitry high temperature reset since HTR was cleared by software HVR – High Voltage Reset Bit 1 = Last reset caused by high voltage detect circuitry high voltage reset since HVR is cleared by software or POR LVR – ...
Page 80
... Freescale Semiconductor, Inc. Technical Data 5.5 Internal Resets The eight internally generated resets are the initial power-on reset function, the COP watchdog timer reset, the illegal address detector, clock-monitor, the high temperature reset, high voltage reset, low-voltage reset, and the disabled STOP instruction. ...
Page 81
... Freescale Semiconductor, Inc. Figure 5-2 RESET and POR Timing Diagram MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Resets Go to: www.freescale.com Resets Power-On Reset (POR) Technical Data ...
Page 82
... Freescale Semiconductor, Inc. Technical Data 5.7 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Regardless of an internal or external reset, the MCU comes out of a COP reset according to the pin conditions that determine mode selection ...
Page 83
... Freescale Semiconductor, Inc. 5.7.3 COP During STOP Mode When the STOP enable mask option is selected, STOP mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter is reset when STOP mode is entered reset is used to exit STOP mode, the COP counter is held in reset during the 4064 cycles of start up delay ...
Page 84
... Freescale Semiconductor, Inc. Technical Data $3FF0 Read: Write: Reset: Figure 5-3 COP Watchdog Timer Location Register (COPR) 5.8 Illegal Address Reset An illegal address reset is generated when the CPU attempts to fetch an instruction from either unimplemented address space ($0100 to $017F, $0200 to $1FFF) monitor ROM ($3F00 to $3FEF) or I/O address space ($0000 to $003F) ...
Page 85
... Freescale Semiconductor, Inc. 5.11 High Voltage Reset The internal high voltage (HVR) reset is generated when the supply voltage V condition remains active until the supply voltage falls below the threshold V HVROFF This reset can be disabled by using a mask option. 5.12 Low Voltage Reset The internal low voltage (LVR) reset is generated when the supply ...
Page 86
... Freescale Semiconductor, Inc. Technical Data backup for the COP system. Because the COP needs a clock to function it is disabled when the clock stops. Therefore, the clock monitor system can detect clock failures not detected by the COP system. Semiconductor wafer processing causes variations of the RC timeout values between individual devices ...
Page 87
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 6.1 Contents 6.2 6.3 6.4 6.5 6.5.1 6.5.1.1 6.5.2 6.6 6.2 Introduction The normal operating mode of the MC68HC(8)05PV8/A is user (or single chip) mode. There is also a monitor mode, primarily for programming and evaluation purposes. In addition to these modes, there are two low power modes which may be entered and exited at will from user mode: STOP and WAIT ...
Page 88
... Freescale Semiconductor, Inc. Technical Data 6.3 User mode Intended mode of operation for executing user firmware. 6.4 Monitor Mode Used for programming the on-chip Program or Data EEPROM (68HC805PV8) and Data EEPROM (68HC05PV8) if desired. 6.5 Low Power Modes The MC68HC(8)05PV8/A is capable of running in one of several low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator ...
Page 89
... Freescale Semiconductor, Inc. 6.5.1.1 Ultra Low Power Mode The Ultra Low Power Mode is only available on the 68HC05PV8A submode to STOP mode. The ULPM bit in the Interrupt Control Register influences the onchip analogue circuits. On setting the ULPM bit, PC0 .. PC4 is forced to input state, PC5/6 is switched off, opamp is debiased, downscaler, power supply and die temperature monitors are disabled ...
Page 90
... Freescale Semiconductor, Inc. Technical Data 1 OSC1 RESET 2 IRQ 3 IRQ INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin. 2. IRQ pin edge-sensitive mask option or Port A pin. 3. IRQ pin level and edge sensitive mask option. Figure 6-1 Stop Recovery Timing Diagram ...
Page 91
... Freescale Semiconductor, Inc. STOP OSCILLATOR AND ALL CLOCKS N OR HVR OR LVR IRQ PORT HVI, LVI Y OSCILLATOR WAIT FOR TIME 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Figure 6-2 STOP and WAIT Flowcharts 6.6 WAIT Mode The WAIT instruction places the MCU in a low-power consumption mode ...
Page 92
... Freescale Semiconductor, Inc. Technical Data During WAIT mode the I bit in the CCR is cleared to enable interrupts. All other registers, memory and input/output lines remain in their previous state. The core timer may be enabled to allow a periodic exit from the WAIT mode. WAIT mode consumes more power than STOP mode. ...
Page 93
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 7. Input/Output Ports Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General Input/Output Programming . . . . . . . . . . . . . . . . . . . . . 94 Port Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port A Pull-up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Port A Voltage Reference for A/D Converter Port A Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 97 Port A Interrupt Status Register ...
Page 94
... Freescale Semiconductor, Inc. Technical Data 7.2 Introduction In single chip mode there are 20 lines arranged as one 8-bit I/O port (port A), one 5-bit I/O port (port B), and one 7-bit high-voltage I/O port (port C). The I/O ports are programmable as either inputs or outputs under software control of the data direction registers (see Input/Output Port A is shared with A/D channels ...
Page 95
... Freescale Semiconductor, Inc. Internal HC05 Connections NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register. NOTE: If the I/O pin is an input and a read-modify-write (RMW) instruction is executed, the I/O pin will be read into the HC05 CPU and the computed result will then be written to the data latch ...
Page 96
... Freescale Semiconductor, Inc. Technical Data 7.4.1 Port A Keyboard Interrupt The keyboard interrupt consists of 8 individual edge-sensitive interrupts with 8 interrupt flags. The keyboard interrupt is generated by a logical OR function of the 8 interrupt flags. The interrupt inputs are connected to PA0–7. All interrupts are maskable. If the interrupt mask bit (I bit) in the condition code register is set, all interrupts are disabled. The interrupts are split in two groups of four lines each (PA0– ...
Page 97
... Freescale Semiconductor, Inc. 7.4.4 Port A Configuration Register $0020 Read: Write: Reset: VRHEN – Enable A/D High Reference Channel Those bits connect the PA7 pin with the A/D high reference channel A/D high reference channel connected to external VREFH A/D high reference channel connected to internal voltage PUHEN – PA4–7 Pull-Up Resistor Enable Higher Nibble This bit disables/enables the pull-up resistors of the PA4– ...
Page 98
... Freescale Semiconductor, Inc. Technical Data PALIE – PA0–3 Interrupt Enable Lower Nibble This bit disables/enables the PA0–3 pins as interrupt group PA0–3 interrupt enabled 0 = PA0–3 interrupt disabled VRLEN – Enable A/D Low Reference Channel This bit connects the PA0 pin with the A/D low reference channel. ...
Page 99
... Freescale Semiconductor, Inc. NOTE: Pull-up resistors on PA4–6 should be disabled when using the operational amplifier Shunt Resistor Figure 7-5 Typical application: positive Vgain amplifier • • • • MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, PA6 PA5 PA4 Figure 7-4 Operational Amplifier ...
Page 100
... Freescale Semiconductor, Inc. Technical Data 7.5 Port B Port 5-bit bidirectional port, shared with timer and PWM channels (TCAP, TCMP, PWM). An XOR function is provided for one timer capture channel. The port B data register is at $0001 and the data direction register (DDR $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs ...
Page 101
... Freescale Semiconductor, Inc. 7.5.2 Port B PWM Channel The port pin PB4 is shared with the PWM channel. In order to connect this pin to the PWM channel, the corresponding bit PWM4 of the I/O configuration register must be set. 7.5.3 I/O Configuration Register $0021 Read: Write: Reset: TXOR – Timer EXOR Enable ...
Page 102
... Freescale Semiconductor, Inc. Technical Data PB2IC – PB2 Input Capture Enable This bit enables the PB2 pin to drive the input capture channel PB2 drives the input capture channel PC2 drives the input capture channel 2 PB1OC – PB1 Output Compare Enable This bit enables the PB1 pin for output compare channel 1 ...
Page 103
... Freescale Semiconductor, Inc. 7.6.1 Port C Timer Channels The port pins PC0–5 are shared with the 16-bit timer channels (TCAP1–2, TCMP1–2). 7.6.2 Port C PWM Channel The port pins PC0, 4–6 are shared with the PWM channel. In order to connect those pins, please refer to Register 0 7 ...
Page 104
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, CSEN&DATA&DDRC CSDT Interrupt DDR DATA CSEN&DATA&DDRC Figure 7-9 PC1–3 Contact Sense Circuitry CSEN&DATA&DDRC CSDT Interrupt ISOMODE DDR DATA Figure 7-10 PC4 Contact Sense Circuitry 68HC(8)05PV8 Input/Output Ports Go to: www.freescale.com ...
Page 105
... Freescale Semiconductor, Inc. Port pin PC0 comprises a circuit that senses the outside resistance R to VSUP. PC4 has a different circuit, which senses the outside resistance R have an universal one, which senses the outside resistance either to VSS or to VSUP, depending on the state of the corresponding data register bit ...
Page 106
... Freescale Semiconductor, Inc. Technical Data Figure 7-12 Principal Characteristic of the Contact Sense Circuitry When setting PCXCS and clearing the corresponding DDR bit, the signal generated by the high voltage input block is used instead of the one of the contact sense block to drive the CSD bits. The CSD ...
Page 107
... Freescale Semiconductor, Inc. the software should take care to switch off the driver as soon as possible whenever a short-circuit occurs. To detect such a condition the PC4CL (Bit 6) in the Interrupt Status Register should be polled. $0029 Read: Write: Reset: MC68HC(8)05PV8 (maskset J47D and J31D): PC4CL - Port C4 in current limit mode ...
Page 108
... Freescale Semiconductor, Inc. Technical Data A permanent external pin voltage above the minimum Zener break-down voltage can destroy the driver. The low side drivers have a short circuit protection feature. Whenever the drain current of the LDMOS transistor exceeds a fixed value, the output is automatically switched off (i.e. the LDMOS is in the high impedance state) and the corresponding short circuit flag is set (SCIF5 or SCIF6) ...
Page 109
... Freescale Semiconductor, Inc. PORT C DATA SCIF5/6 Figure 7-15 Short Circuit Diagnostic of Port C Low Side Driver 7.6.6 Port C Configuration Register 0 $0022 Read: Write: Reset: Figure 7-16 Port C Configuration Register 0 (PCCFG0) ISOM – Driver Mode of PC4 This bit selects the driver mode of PC4. The ISOM bit is without function on 68HC05PV8A ...
Page 110
... Freescale Semiconductor, Inc. Technical Data PWMS1, PWMS0 – PWM Select Bits These bits select the output pin for the PWM on PC0, PC4 or PC5. PC3OC – PC3 Output Compare Enable This bit enables the PC3 pin for output compare channel PC3 output compare channel 2 enabled. PC3 DDR bit must PC3 output compare channel 2 disabled TS2, TS1, TS0 – ...
Page 111
... Freescale Semiconductor, Inc. To enable either PWM or output compare function the corresponding DDR bit must be set PWM and timer output compare functions are routed to the same pin, PC0 and PC4 would be connected to the output compare signal, PC5 would be connected to the PWM signal. ...
Page 112
... Freescale Semiconductor, Inc. Technical Data TXOR TIC1 TIC2 TOC2 PWM TOC1 Port C Data 0 Port C Data 1 Port C Data 2 Port C Data 3 Port C Data 4 Port C Data 5 Port C Data 6 Figure 7-17 Port C Special Signal Routing Technical Data For More Information On This Product, PB0 PB0OC TS2,1,0 PB2OC ...
Page 113
... Freescale Semiconductor, Inc. 7.6.7 Port C Configuration Register 1 $0026 Read: Write: Reset: Figure 7-18 Port C Configuration Register 1 (PCCFG1) CSIE – Port C Contact Sense Interrupt Enable This bit enables contact sense interrupt of the lines PC4– Port C contact sense interrupt enabled 0 = Port C contact sense interrupt disabled SCIE6 – ...
Page 114
... Freescale Semiconductor, Inc. Technical Data PC1CS – PC1 Contact Sense Enable This bit enables the PC1 contact sense circuitry PC1 contact sense circuitry enabled 0 = PC1 contact sense circuitry disabled PC0CS – PC0 Contact Sense Enable This bit enables the PC0 contact sense circuitry. ...
Page 115
... Freescale Semiconductor, Inc. SCIF5 – Low Side Driver Short Circuit Interrupt Flag This flag indicates a short circuit on PC5 is active and an interrupt request is pending Short circuit at the PC5 pin; PC5 is switched to high impedance short circuit at the PC5 pin CSD4 – PC4 Contact Sense Data This data bit represents the result of the PC4 contact sense circuitry ...
Page 116
... Freescale Semiconductor, Inc. Technical Data 7.6.9 MFTEST Register $002F Read: Write: Reset: HVTOFF – Disable of Port C Inputs This data bit controls the operation of the Port C Inputs 1 = Port C High Voltage Inputs (PC0 - PC4) disabled 0 = Port C High Voltage Inputs enabled VSCAL – Disable of V This data bit controls the operation of the V ...
Page 117
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 8.1 Contents 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.2 Introduction The core timer for this device is a 15-stage multi-functional ripple counter. The features include timer over flow, power-on reset (POR), real time interrupt (RTI), and COP watchdog timer. As seen in circuit followed by a fixed divide by four pre-scaler. This signal drives an 8-bit ripple counter ...
Page 118
... Freescale Semiconductor, Inc. Technical Data RTI and TOF enable bits and flags are located in the timer status and control register at location $08 TCR Overflow Detect Circuit TCSR TOF RTIF TOFE RTIE To Interrupt Figure 8-1 Core Timer Block Diagram Technical Data ...
Page 119
... Freescale Semiconductor, Inc. 8.3 Registers 8.3.1 Core Timer Status & Control Register (CTSCR) The CTSCR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. value of each bit in the CTSCR when coming out of reset. $0008 ...
Page 120
... Freescale Semiconductor, Inc. Technical Data RTOF – Reset TOF This bit always reads 0. Setting this bit clears the timer overflow flag (TOF). Clearing this bit has no effect. RRTIF – Reset RTIF This bit always reads 0. Setting this bit clears the real time interrupt flag (RTIF). Clearing this bit has no effect. RT1, RT0 – ...
Page 121
... Freescale Semiconductor, Inc. 8.3.2 Computer Operating Properly (COP) Watchdog Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in out, an internal reset is generated and the normal reset vector is fetched. ...
Page 122
... Freescale Semiconductor, Inc. Technical Data The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin ...
Page 123
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 9.1 Contents 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 9. 16-Bit Programmable Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Registers 126 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 127 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .129 Timer Control Register 131 Timer Control Register 132 Timer Status Register ...
Page 124
... Freescale Semiconductor, Inc. Technical Data 9.2 Introduction The MC68HC(8)05PV8/A has one 16-bit timer with two channels. The timer consists of a 16-bit free running counter driven by a fixed divide-by-four pre-scaler. This timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform ...
Page 125
... Freescale Semiconductor, Inc. Internal Bus 8-BIT Clock BUFFER High Low High 4 Byte Byte Byte 16-BIT FREE $18 OUTPUT RUNNING COMPARE $19 COUNTER $1A COUNTER ALTERNATE $1B REGISTER OVERFLOW OUTPUT DETECT COMPARE ICI1E ICI2E OCI1E TOFIE OCI2E - - TOFF TCR1 $1C Interrupt TCAP2 TCAP1 MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 126
... Freescale Semiconductor, Inc. Technical Data 9.3 Registers 9.3.1 Counter The key element in the programmable timer is a 16-bit free-running counter or counter register, preceded by a pre-scaler that divides the internal processor clock by four. The pre-scaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock ...
Page 127
... Freescale Semiconductor, Inc. 9.3.2 Output Compare Registers There are two output compare registers: Output compare register 1 and output compare register 2. Output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. All bits are readable and writeable and are not altered by the timer hardware or reset ...
Page 128
... Freescale Semiconductor, Inc. Technical Data Because the output compare flag OC1F and the output compare register 1 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function. The following procedure is recommended. Write the high byte to the compare register 1 to inhibit further compares until the low byte is written ...
Page 129
... Freescale Semiconductor, Inc. The processor can write to either byte of the output compare register 2 without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register regardless of whether the output compare flag (OC2F) is set or clear. Because the output compare flag OC2F and the output compare register 2 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function ...
Page 130
... Freescale Semiconductor, Inc. Technical Data The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC1F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture ...
Page 131
... Freescale Semiconductor, Inc. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC2F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. ...
Page 132
... Freescale Semiconductor, Inc. Technical Data OCI2E – Output Compare 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOFF – Shut Off Timer 1 = Timer is disabled. This can be used to save power if timer is not 0 = Timer is enabled 9.3.5 Timer Control Register 2 $001D Read: Write: Reset: IEDG1 – Input Edge Value of input edge determines which level transition on TCAP1 pin will trigger free running counter transfer to the input capture register 1 ...
Page 133
... Freescale Semiconductor, Inc. FOLV1 – Force Output Level 1 The FOLV1 bit always reads as zero. Writing a zero at this position has no effect. Writing a one at this position will force the OLVL1 bit to the corresponding output level latch, thus appearing at pin TCMP1. Note that the force output compare 1 does not affect the OCF1 bit of the status register. OLVL1 – ...
Page 134
... Freescale Semiconductor, Inc. Technical Data 9.3.6 Timer Status Register The timer status register is a read-only register containing timer status flags. $001E Read: Write: Reset: IC1F – Input Capture 1 Flag 1 = Flag set when selected polarity edge is sensed by input capture 0 = Flag cleared when TSR and input capture 1 registers low byte IC2F – ...
Page 135
... Freescale Semiconductor, Inc. SI1 – Sample Input Bit set when input capture 1 input is sampled high while output 0 = Bit cleared when input capture 1 input is sampled low while SI2 – Sample Input Bit set when input capture 2 input is sampled high while output ...
Page 136
... Freescale Semiconductor, Inc. Technical Data 9.4 Timer During WAIT Mode The CPU clock halts during WAIT mode but the timer keeps on running. If any reset is used to exit WAIT mode the counters are forced to $FFFC. If interrupts are enabled a timer interrupt will cause the processor to exit WAIT mode ...
Page 137
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.6.1 10.6.2 10.7 10.8 10.9 10.10 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 10.10.2 10.10.3 10.10.4 10.10.5 10.10.6 10.10.7 10.10.8 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 10. Analog to Digital Converter Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal and Master Oscillator 139 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 A/D Status and Control Register (ADSCR 140 A/D Data Register ...
Page 138
... Freescale Semiconductor, Inc. Technical Data 10.2 Introduction The analog to digital converter system consists of a single 8-bit successive approximation converter and a channel multiplexer. There is one 8-bit result data register and one 8-bit status/control register. The reference supply can be switched by software either to the internal VDD and VSS supplies or to external pins individually ...
Page 139
... Freescale Semiconductor, Inc. 10.4 A/D Operation The A 8-bit successive approximation register (SAR) type A/D converter with continuous conversion per given channel. The result of a conversion is loaded into the read-only result data register and a conversion complete flag COCO is set in the A/D status/control register. Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel ...
Page 140
... Freescale Semiconductor, Inc. Technical Data 3. 10.6 A/D Registers 10.6.1 A/D Status and Control Register (ADSCR) The following paragraphs describe the function of the A/D status and control register. $000F Read: Write: Reset: Figure 10-1 A/D Status and Control Register (ADSCR) COCO – Conversion Complete This read-only status bit is set when a conversion is completed, indicating that the A/D data register contains valid results ...
Page 141
... Freescale Semiconductor, Inc. ADON – A/D On When the A/D is turned on (ADON = 1), it requires a time t the current sources to stabilize, and results can be inaccurate during this time. This bit turns on the charge pump. ADTST This bit is for test purposes only. Write only 0. CH3:0 – Channel Select Bit CH3, CH2, CH1 and CH0 form a four bit field which is used to select one of sixteen A/D channels. Channels 8– ...
Page 142
... Freescale Semiconductor, Inc. Technical Data CH3 NOTE: Channel 0 and 7–15 convert internal signals which cannot be accessed externally. 10.6.2 A/D Data Register One 8-bit result register is provided. This register is updated each time COCO is set. $000E Read: Write: Reset: 10.7 A/D During WAIT Mode The A/D converter continues normal operation during WAIT mode. To ...
Page 143
... Freescale Semiconductor, Inc. 10.8 A/D During STOP Mode In STOP mode the comparator and charge pump are turned off and the A/D ceases to function. Any pending conversion is aborted. When the clocks begin oscillation upon leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize enough to provide conversions to the specified accuracy ...
Page 144
... Freescale Semiconductor, Inc. Technical Data INPUT PROTECTION PA1... PA6 < 10pF * THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME Figure 10-4 Electrical Model of an A/D Input Pin Be sure that pins used as analog inputs are configured as inputs with their appropriate pull-up resistors disabled (enabled after reset). ...
Page 145
... Freescale Semiconductor, Inc. Figure 10-5 Transfer Curve of an Ideal 8-Bit A/D Converter 10.10.2 Monotonicity The characteristic of the transfer function whereby increasing the input signal results in the output never decreasing. 10.10.3 Quantization Error Also known as digitization error or uncertainty the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input ...
Page 146
... Freescale Semiconductor, Inc. Technical Data 10.10.4 Offset Error The offset error is the DC shift of the entire transfer curve of an ideal converter. 10.10.5 Gain Scale Error The gain error is an error in the input to output transfer ratio. Gain error causes an error in the slope of the transfer curve. ...
Page 147
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.6 11.7 11.8 11.2 Introduction The pulse width modulator (PWM) system has one channel. The PWM has a programmable period of PWMPRxT = PWMPR / f PWMPR is a programmable period (1... 256) and 1/f OSC frequency. MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 11 ...
Page 148
... Freescale Semiconductor, Inc. Technical Data OSC1 Clock Generator 11.3 Functional Description The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data register yields an OFF output (0%), but an $FF yields a duty of 255/256 (assuming the PWM period register is set to $FF). To achieve the 100% duty (ON output), the polarity control bit is set while the data register contains $00 ...
Page 149
... Freescale Semiconductor, Inc. conversion n–1 complete Figure 11-2 PWM Waveforms (POL = 0, active low), PWMPR = $FF (PWMPR - PWMDAT conversion n–1 complete Figure 11-3 PWM Waveforms (POL = 1, active high), PWMPR = $CF MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, (PWMPR + PWM PWMDAT = $00 (PWMPR + PWM A0 PWMDAT = $FF ( > ...
Page 150
... Freescale Semiconductor, Inc. Technical Data 11.4 Registers Associated with the PWM system, there are a PWM data register, a PWM period register and a PWM control register. These registers can be written to and read at any time. Writing to the data or the period register takes effect when the whole PWM system is started by switching on the PWMON bit or when a conversion cycle is complete ...
Page 151
... Freescale Semiconductor, Inc. PRA3, PRA2, PRA1, PRA0 – PWM Clock Rate Bits These bits select the input clock rate f Table The PWM clock rate bits are not latched until the end of conversion. They affect the PWM output immediately. For proper operation these control bits must not be changed during conversion ...
Page 152
... Freescale Semiconductor, Inc. Technical Data 11.4.3 PWM Period Register The PWM system has an 8-bit period register that holds the PWM period. The frame frequency of the PWM system is defined frame This register can be written at any time. The period of the output changes after the current cycle. ...
Page 153
... Freescale Semiconductor, Inc. 11.8 Frame Frequency Examples PRA3–PRA0 0000 0001 0010 0111 PRA3–PRA0 0000 0001 0010 0111 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Table 11-2 Frame Frequency for f PWMPR = $10 PWMPR = $40 247KHz 64.5KHz 165KHz 43KHz 123KHz 32.3KHz 20.6KHz 5.38KHz ...
Page 154
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Pulse Width Modulator Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 155
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 12.1 Contents 12.2 12.3 12.4 12.5 12.2 Introduction The MC68HC(8)05PV8/A contains a low-power, low-drop CMOS on-chip fixed voltage regulator to provide internal power to the MCU from an external DC source. The MC68HC05PV8A contains on top of that a selectable standby regulator to achieve lower standby current. ...
Page 156
... Freescale Semiconductor, Inc. Technical Data Any loss of V reset. The device remains in the reset state for the duration of the LVR condition or until the internal V device, at which point reset no longer has meaning. If the drop in V that triggers an LVR is transient, then an internal RST is asserted for a minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay) ...
Page 157
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 13.1 Contents 13.2 13.3 13.4 13.5 13.5.1 13.5.2 13.5.3 13.6 13.2 Introduction The EEPROM on this device is 128 bytes and is located from address $0180 to $01FF. The user programs the EEPROM on a single-byte basis by manipulating the EEPROM control register (EEPCR). An erased byte reads as $FF and any programmed bit reads as 0. ...
Page 158
... Freescale Semiconductor, Inc. Technical Data 13.3 EEPROM Control Register (EEPCR) $000C Read: Write: Reset: EEOSC – EEPROM RC Oscillator Control When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. The user must wait a time t after setting the EEOSC bit to allow the RC oscillator to stabilize. ...
Page 159
... Freescale Semiconductor, Inc. EELAT – EEPROM Programming Latch The EELAT bit is the EEPROM programming latch enable. When EELAT the EER1, EER0 and EEPGM bits are reset to zero. When the EELAT bit is clear, data can be read from the EEPROM. When set, this bit allows the address and data to be latched into the EEPROM for further programming or erase operation ...
Page 160
... Freescale Semiconductor, Inc. Technical Data register. When this bit is set from (erased) the protection remains until the next power-on or external reset. EEPRT can only be written to 0 when the ELAT bit in the EEPROM control register is set Block 2 of the EEPROM array is not protected; all 128 bytes Block 2 of the EEPROM array is protected ...
Page 161
... Freescale Semiconductor, Inc. a programming operation, any access of EEPROM will return $FF. To program a second byte, EELAT must be cleared before it is set, otherwise the programming will have no effect. 13.6 Operation in STOP and WAIT Modes The RC oscillator for the EEPROM is automatically disabled when entering STOP mode. The user may want to ensure that the RC oscillator is disabled before entering WAIT mode to help conserve power ...
Page 162
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, EEPROM Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 163
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 14.1 Contents 14.2 14.3 14.4 14.5 14.2 Introduction The Program EEPROM on the MC68HC805PV8 is 7936 bytes and is located from address $2000 to $3EFF. It also holds 16 bytes of user vectors ranging from $3FF0 to $3FFF. Programming circuitry embedded in the EEPROM block allows a group four different bytes to be written or erased simultaneously ...
Page 164
... Freescale Semiconductor, Inc. Technical Data 14.3 Programming Register Three bits of the program EEPROM programming register have been provided in order to control the EEPROM operations. $000D Read: Write: Reset: Figure 14-1 Program EEPROM Control Register (PEECR) RCON – RC Oscillator On This bit determines the state of the RC oscillator. This oscillator should be switched on when the device is operated below 1MHz bus clock ...
Page 165
... Freescale Semiconductor, Inc. controls the activation of the charge pump. The charge pump is not affected by WAIT mode, thus it is possible to wait the read mode when entering STOP mode EEPROM read state 0 = Activate charge pump; address and data may be latched for PGMB – Programming enable When cleared, this bit allows programming of the EEPROM ...
Page 166
... Freescale Semiconductor, Inc. Technical Data 14.5 Options Register The options register (OPTR), which also contains the protect function for the Program EEPROM in the MC68HC805PV8 version, is located at $2000 and allows the user to select options in a non-volatile manner. The contents of the OPTR register are loaded into data latches with each reset ...
Page 167
... Freescale Semiconductor, Inc. CME – Clock Monitor Enable The CME bit enables a watchdog for the oscillator circuit. When the frequency drops below a threshold (due to a brown-out or a defective element), when enabled, the clock monitor will reset the MCU and switch to an internal RC oscillator. ...
Page 168
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Program EEPROM Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 169
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 15.1 Contents 15.2 15.3 15.3.1 15.2 Introduction The MC68HC(8)05PV8/A includes a fast parallel interface to access external peripheral components as fast as internal ones. The external address space ranges from $0030 to $003F and all 68HC05 instructions can be applied to this memory. Since the data path is only 4-bits wide either the lines PA7– ...
Page 170
... Freescale Semiconductor, Inc. Technical Data PB0 AS PB1 PB2 PB3 PA0-3 Figure 15-1 Basic Fast Peripheral Interface Timing The basic timing as shown in the HC11 parts in expanded multiplex mode. At the falling edge of the address strobe signal (AS/PB0) the addresses on PA0–3, the read/write signal (RW/PB1) and the chip select (CS/PB3) signal are valid. A high DEN/PB2 signal indicates that data are driven on the bus in CPU write cycles or that the peripheral IC can drive data in read cycles ...
Page 171
... Freescale Semiconductor, Inc. 15.3.1 System Control Register The following paragraphs describe the FPIE and FPICLK bit function of the system control register. $000A Read: Write: Reset: FPIE – Fast Peripheral Interface Enable If this bit is set the fast peripheral interface is enabled. PA0–3 and PB0– ...
Page 172
... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Fast Parallel Interface Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
Page 173
... Freescale Semiconductor, Inc. Technical Data — MC68HC(8)05PV8/A 16.1 Contents 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.9.1 16.10 Down Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 Die Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 Fast Peripheral Interface Timing 188 16.15 PORT C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 16.15.2 16.15.3 16.15.5 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, Section 16. Electrical Specifications Maximum Ratings ...
Page 174
... Freescale Semiconductor, Inc. Technical Data 16.2 Maximum Ratings (Voltages referenced Rating Supply Voltage Supply Voltage without using the Voltage Regulator ( SUP DD Input Voltage (PA0–7, PB0–4, OSC1) Input Voltage (IRQ, RESET) Input Voltage (PC0–3) Input Voltage (PC4) Applied Voltage (PC5/6) ...
Page 175
... Freescale Semiconductor, Inc. 16.3 Thermal Characteristics Characteristic Thermal Resistance SOIC28 16.4 Program and Data EEPROM Characteristics (V = 5.0Vdc 10 0Vdc Rating Write/Erase Cycles Program EEPROM @ 10ms write time +125 C J Write/Erase Cycles Data EEPROM @ 10ms write time +125 C J Data Retention EEPROMs Program EEPROM Programming Time per 4 Bytes ...
Page 176
... Freescale Semiconductor, Inc. Technical Data 16.5 Supply Current (6V V 16V, device untrimmed, V SUP Characteristic Full circuit in Run mode TIMER, A/D, PWM, COP on Full circuit in Wait mode TIMER, A/D, PWM, COP on TIMER, A/D, PWM, COP off Full circuit in Stop mode (PV8) Port C, Op Amp, Power Supply Monitor, Temperature ...
Page 177
... Freescale Semiconductor, Inc. the VSCAL bit in the MFTEST register. 7. Low Side Drivers and Die Temperature Monitor can be disabled by setting LSOFF bit in the MFTEST register. 8. The Die Temperature Monitor is only disabled when the LSOFF bit is set and the Port C4 DDR bit is cleared as well. ...
Page 178
... Freescale Semiconductor, Inc. Technical Data 16.6 V Referenced Pins Electrical Characteristics 5.0Vdc 10 0Vdc Characteristic Output Low Voltage Port A, Port B Output Low Voltage RESET Output High Voltage Port A, Port B Input High Voltage Port A, Port B, IRQ, RESET, OSC1 Input Low Voltage Port A, Port B, IRQ, RESET,OSC1 ...
Page 179
... Freescale Semiconductor, Inc. NOTES: (see next page) 1. The pull-up structures on Port A0–7 can be disabled by software, they are automatically enabled by each reset. 2. The pull-up structures on Port A consist of enabled PMOS devices. For input voltages near simple protection can be built with a series resistor: R > V during multiple injection should be limited below the maximum values for a single pin: R > ...
Page 180
... Freescale Semiconductor, Inc. Technical Data 16.7 Voltage Regulator (6V V 16V, device untrimmed, V SUP Characteristic Output Voltage (6V V 16V) SUP Output Voltage (9V V 16V) in SUP Ultra Low Power Mode Output Voltage (5.5V < V 40V) SUP Total Output Current Line Regulation (6V V 16V) SUP Load Regulation ...
Page 181
... Freescale Semiconductor, Inc RESET Figure 16-1 Low Voltage Reset waveform MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product LVRON V LVRON Electrical Specifications Go to: www.freescale.com Electrical Specifications Voltage Regulator LVRH Technical Data ...
Page 182
... Freescale Semiconductor, Inc. Technical Data 16.8 Operational Amplifier (device untrimmed 0Vdc Characteristic Input Offset Voltage Input Common Mode Voltage Range Large Signal Gain Output Voltage Swing Output Short Circuit Current Output Short Circuit Current Slew Rate Gain Bandwidth Product ...
Page 183
... Freescale Semiconductor, Inc. 16.9 Power Supply Monitor 16.9.1 V related Reset and Interrupts SUP (device untrimmed 0Vdc Characteristic High Voltage Reset On High Voltage Reset Hysteresis High Voltage Interrupt On High Voltage Interrupt Hysteresis Low Voltage Interrupt On Low Voltage Interrupt Hysteresis NOTE: See chapter V HVRON V – ...
Page 184
... Freescale Semiconductor, Inc. Technical Data 16.10 Down Scaler (device untrimmed 0Vdc Characteristic Voltage Ratio V /V SUP AD7 NOTE: 1. The Down Scaler output is internally clamped at 5.3V typical. 2. The Down Scaler can only be observed by the A/D. The errors of the A/D has to be taken into account. 16.11 Die Temperature Monitor ...
Page 185
... Freescale Semiconductor, Inc. 16.12 Control Timing (V = 5.0Vdc 10 0Vdc Characteristic Frequency of Operation Crystal Oscillator Option (i.e. using the oscillator with a crystal) External Clock Source Oscillator Frequency With Enabled Clock Monitor Cycle Time (2/f ) OSC Frequency Detected As Clock Monitor Error Clock Monitor Backup-Oscillator Frequency ...
Page 186
... Freescale Semiconductor, Inc. Technical Data OSC1 RESET t ILIH 2 IRQ 3 IRQ Internal Clock Internal Address Bus NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive selected. 3. IRQ pin level and edge-sensitive selected. 4.RESET vector address shown for timing example. ...
Page 187
... Freescale Semiconductor, Inc. 16.13 A/D Converter Characteristics ( 5.0Vdc 10%, V REFH DD REFL Characteristic Resolution Absolute Accuracy Conversion Range Voltage Reference High Level Voltage Reference Low Level Analog Input Voltage Zero Input Reading Full-scale Reading Conversion Time (Including Sampling Time) Sampling Time Power-up Time ...
Page 188
... Freescale Semiconductor, Inc. Technical Data 16.14 Fast Peripheral Interface Timing (V = 5.0Vdc 10 0Vdc Characteristic DEN/AS Rise and Fall Time Pulse Width AS, DEN high Address, CS, RW setup time Address, CS, RW hold time Read data setup time Read data hold time Write data setup time ...
Page 189
... Freescale Semiconductor, Inc. 16.15 PORT C Characteristics 16.15.1 High Voltage Input/Output (PC0–4) (6V V 16V, device untrimmed, V SUP Characteristic Symbol Input Low Voltage Input High Voltage Input Hysteresis Voltage (PC0-3, PC4 on MC68HC(8)05PV8) Leakage Current Input Pull-Down Current I P ULL Output Low Voltage (PC0–3) Output High Voltage (PC0– ...
Page 190
... Freescale Semiconductor, Inc. Technical Data 16.15.3 ISO9141 Driver (PC4) MC68HC(8)05PV8 (6V V 16V, device untrimmed, V SUP Characteristic Output Falling Edge Slew Rate Output Rising Edge Slew Rate Rise Fall Slew Rates Symmetry Output Low Voltage Leakage Current (driver switched recessive) Current Limitation Threshold NOTES: 1 ...
Page 191
... Freescale Semiconductor, Inc. 16.15.5 Low Side Driver (PC5/6, PVSS) (6V V 16V, device untrimmed, Vss = 0 Vdc, T SUP Characteristic Output Resistance Leakage Current Positive Output Clamp Voltage Over Current Threshold Shutdown MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, = – +125 C, unless otherwise noted) ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Electrical Specifications Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. B.1 (6V unless otherwise noted) Characteristic Output Current NOTE : 1. With an external serial resistor 82.6 MC68HC(8)05PV8/A — Rev. 1.9 For More Information On This Product, APPENDIX B ELECTRICAL SPECIFICATION FOR CURRENT COMMUNICATION INTERFACE Current Interface (PC5 or 6, PVSS) V 16V, device untrimmed Vss = 0 Vdc, T SUP ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Go to: www.freescale.com MC68HC(8)05PV8/A — Rev. 1.9 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...