CY62256VL-70ZC Cypress Semiconductor Corporation., CY62256VL-70ZC Datasheet

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CY62256VL-70ZC

Manufacturer Part Number
CY62256VL-70ZC
Description
32K x 8 static RAM, 70ns, wide voltage range: 2.7V-3.6V, L-power
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Features
Functional Description
The CY62256V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE) and active
Cypress Semiconductor Corporation
• 55, 70 ns access time
• CMOS for optimum speed/power
• Wide voltage range: 2.7V 3.6V
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
— 108 mW (max.)
— 18 W (max.)
WE
OE
CE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
INPUT BUFFER
512x512
DECODER
COLUMN
ARRA Y
POWER
DOWN
3901 North First Street
PRELIMINARY
C62256V–1
LOW output enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 98% when deselected. The CY62256V is in
the standard 450-mil-wide (300-mil body width) SOIC, TSOP,
and reverse TSOP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
7
San Jose
) is written into the memory location addressed by
Pin Configurations
32K x 8 Static RAM
GND
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
March 1996 – Revised May 1996
CA 95134
13
14
1
2
3
4
5
6
7
8
9
10
11
12
Top View
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY62256V
I/O
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
CC
4
3
2
1
0
fax id: 1069
0
3
7
6
5
4
C62256V–2
408-943-2600
through A
14
).
0

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CY62256VL-70ZC Summary of contents

Page 1

Features • 55 access time • CMOS for optimum speed/power • Wide voltage range: 2.7V 3.6V • Low active power (70 ns, LL version) — 108 mW (max.) • Low standby power (70 ns, LL version) — 18 ...

Page 2

Pin Configurations (continued ...

Page 3

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Load Current IX I Output Leakage Current OZ I Output ...

Page 4

Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [3] t Chip Deselect to Data CDR Retention Time [3] t Operation Recovery Time R Data Retention Waveform Switching Characteristics ...

Page 5

Switching Characteristics Over the Operating Range Parameter [8,9] WRITE CYCLE t Write Cycle Time LOW to Write End SCE t Address Set-Up to Write End AW t Address Hold from Write End HA t Address Set-Up to ...

Page 6

Switching Waveforms (continued) [8, 13, 14] Write Cycle No. 1 (WE Controlled) ADDRESS NOTE 15 DATA I/O t HZOE [8, 13, 14] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle ...

Page 7

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.40 1. 1.00 0.80 0.60 V =3. = 0.40 0. 0.00 2.70 3.00 3.30 3.60 3.90 SUPPLY VOLTAGE (V) NORMALIZED ACCESS ...

Page 8

... CY62256V-55SNC CY62256VL-55SNC CY62256VLL-55SNC CY62256V-55RZC CY62256VL-55RZC CY62256VLL-55RZC CY62256V-55ZC CY62256VL-55ZC CY62256VLL-55ZC 70 CY62256V-70SNC CY62256VL-70SNC CY62256VLL-70SNC CY62256V-70RZC CY62256VL-70RZC CY62256VLL-70RZC CY62256V-70ZC CY62256VL-70ZC CY62256VLL-70ZC Shaded area contains advanced information. Document #: 38-00519 PRELIMINARY Mode Power Standby (I SB Active (I CC Active (I CC Active (I CC Package Name Package Type S22 ...

Page 9

Package Diagrams 28-Lead 450-Mil (300-Mil Body Width) SOIC S22 PRELIMINARY 28-Lead Reverse Thin Small Outline Package RZ28 9 CY62256V ...

Page 10

Package Diagrams (continued) © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor ...

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