CY62256L-70ZI Cypress Semiconductor Corporation., CY62256L-70ZI Datasheet

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CY62256L-70ZI

Manufacturer Part Number
CY62256L-70ZI
Description
32K x 8 static RAM, 70ns, L-power
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Functional Description
The CY62256 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
Cypress Semiconductor Corporation
• 4.5V–5.5V Operation
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• 55, 70 ns access time
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Logic Block Diagram
C62256–1
— 275 mW (max.)
— 28 W (max.)
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
V
A
A
WE
OE
CC
A
A
A
A
A
A
A
A
A
11
10
9
8
6
5
4
3
2
1
7
26
25
24
23
22
7
6
5
4
3
2
1
28
27
INPUTBUFFER
512x512
DECODER
COLUMN
ARRA Y
Reverse Pinout
(not to scale)
Top View
TSOP I
POWER
DOWN
3901 North First Street
10
11
12
13
14
15
16
17
18
19
20
21
8
9
C62256–4
A
A
A
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
CE
A
12
13
14
0
0
1
2
3
4
5
6
7
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consump-
tion by 99.9% when deselected. The CY62256 is in the stan-
dard 450-mil-wide (300-mil body width) SOIC, TSOP, and
600-mil PDIP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
V
WE
A
A
OE
CC
A
A
A
A
A
A
A
A
A
10
11
1
2
3
4
5
6
8
9
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
22
23
24
25
26
4
5
6
7
27
28
1
2
3
7
San Jose
) is written into the memory location addressed by
March 1996 – Revised November 26, 1997
(not to scale)
Top View
TSOP I
Pin Configurations
GND
I/O
I/O
I/O
A
A
A
A
A
32Kx8 Static RAM
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
CA 95134
13
14
1
2
3
4
5
6
7
8
9
10
11
12
SOIC/DIP
Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
21
20
19
18
17
16
15
14
13
12
11
10
9
8
CY62256
C62256–3
I/O
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
CC
4
3
2
1
0
fax id: 1068
0
0
14
13
12
3
7
6
5
4
408-943-2600
7
6
5
4
3
2
1
0
through A
C62256–2
14
).
0

Related parts for CY62256L-70ZI

CY62256L-70ZI Summary of contents

Page 1

Features • 4.5V–5.5V Operation • Low active power (70 ns, LL version) — 275 mW (max.) • Low standby power (70 ns, LL version) — (max.) • 55 access time • Easy memory expansion with CE ...

Page 2

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature Ambient Temperature with Power Applied ................................................... +70 C Supply Voltage to Ground Potential (Pin 28 to Pin 14) DC ...

Page 3

AC Test Loads and Waveforms R1 1800 5V OUTPUT OUTPUT R2 100 pF 990 INCLUDING INCLUDING JIG AND SCOPE (a) Equivalent to: THÉ VENIN EQUIVALENT 639 OUTPUT Data Retention Characteristics Parameter Description V V for Data Retention ...

Page 4

Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

Page 5

Switching Waveforms (continued) [11,12] Read Cycle No ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Write Cycle No. 1 (WE Controlled) ADDRESS DATA I/O ...

Page 6

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 15 t HZWE Note: 15. During this period, the I/Os are in output state and input signals should not be applied. ...

Page 7

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0.8 0.6 V =5. = 0.4 0 0.0 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS ...

Page 8

Typical DC and AC Characteristics TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) Truth Table Inputs/Outputs High ...

Page 9

... CY62256L 70SNC CY62256LL 70SNC CY62256–70SNI CY62256L–70SNI CY62256LL 70SNI CY62256 70ZC CY62256L 70ZC CY62256LL 70ZC CY62256–70ZI CY62256L 70ZI CY62256LL 70ZI CY62256 70PC CY62256L 70PC CY62256LL 70PC CY62256 70ZRC CY62256L 70ZRC CY62256LL 70ZRC Shaded area contains preliminary information. Document #: 38 00455 C ...

Page 10

Package Diagrams 28-Lead (600-Mil) Molded DIP P15 28-Lead 450-Mil (300-Mil Body Width) SOIC S22 10 CY62256 ...

Page 11

Package Diagrams (continued) 28-Lead Thin Small Outline Package Z28 11 CY62256 ...

Page 12

Package Diagrams (continued) 28-Lead Reverse Thin Small Outline Package ZR28 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry ...

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