HY5DV281622DT-5 Hynix Semiconductor, HY5DV281622DT-5 Datasheet
HY5DV281622DT-5
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HY5DV281622DT-5 Summary of contents
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... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Aug. 2003 HY5DV281622DT HY5DV281622DT ...
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... Revision History Revision No. 0.1 Defined Preliminary Specification 0.2 Defined Target AC, DC spec. 0.3 Changed tCK_max. value of HY5DV281622DT-4/5/6 from 7.5ns to 7.0ns 0.4 Changed VDD/VDDQ max range of HY5DV281622DT-33/36 0.5 Changed tRAS_max Value from 120K to 100K in All Frequency Rev. 0.5 / Aug. 2003 History HY5DV281622DT Draft Date Remark May. 2002 Nov. 2002 Feb ...
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... Part No. Power Supply HY5DV281622DT-33 HY5DV281622DT- HY5DV281622DT-4 V DDQ HY5DV281622DT-5 HY5DV281622DT-6 Rev. 0.5 / Aug. 2003 power supply • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Write mask byte controls by LDM and UDM • ...
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... NC 25 BA0 26 BA1 27 A10/ ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh HY5DV281622DT DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 55 ...
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... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DV281622DT 5 ...
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... Rev. 0.5 / Aug. 2003 Write Data Register 2-bit Prefetch Unit 32 Bank 2Mx16/Bank0 Control 2Mx16/Bank1 2Mx16/Bank2 2Mx16/Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL DLL CLK Block Mode Register HY5DV281622DT DQ[0:15] LDQS, UDQS Data Strobe Transmitter Data Strobe DS Receiver 6 ...
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... HY5DV281622DT A10/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.5 / Aug. 2003 CKEn /CS, /RAS, /CAS, / HY5DV281622DT A10/ LDM UDM ADDR ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DV281622DT Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DV281622DT Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP HY5DV281622DT Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DV281622DT Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... HY5DV281622DT /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DV281622DT SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.5 / Aug. 2003 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DV281622DT < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DV281622DT AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command. Rev. 0.5 / Aug. 2003 HY5DV281622DT 17 ...
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BA1 BA0 A12 A11 A10 0 0 Operating Mode BA0 MRS Type 0 MRS 1 EMRS A12~ A6~ Valid Valid ...
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... HY5DV281622DT Interleave ...
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... The HY5DV281622D supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength. Rev. 0.5 / Aug. 2003 HY5DV281622DT 20 ...
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... An~A3 A2~A0 0 Valid This part do not support/QFC function, A2 must be programmed to Zero. Rev. 0.5 / Aug. 2003 Operating Mode Operating Mode Noraml Operation All other states reserved HY5DV281622DT DLL A0 DLL enable 0 Enable 1 Diable Output Driver A1 Impedance Control 0 Full Strength Driver ...
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... VDDQ+0.3 VID(DC) 0.36 VDDQ+0.6 VI(RATIO the transmitting device, and to track variations in the dc level of the same. DDQ ± the dc value. HY5DV281622DT Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Typ. Max Unit 3.3 3.45 V 3.3 3.65 V 2.5 2.625 V 2.5 3. ...
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... Note : 3.6V, All other pins are not tested under V IN Rev. 0.5 / Aug. 2003 (TA=0 to 70oC, Voltage referenced to V Symbol Min 0. 0V HY5DV281622DT = 0V) SS Max Unit 0. disabled 2.7V OUT OUT Note -15 ...
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... DD5 CKE=<0.2V; External clock on; Self Refresh Current I DD6 tCK=tCK(min) Operating Current - I Four bank interleaving with BL=4 DD7 Four Bank Operation Rev. 0.5 / Aug. 2003 o (TA Voltage referenced to V Test Condition HY5DV281622DT = 0V) SS Speed 150 140 130 120 100 170 150 ...
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... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DV281622DT = 0V) SS Max Unit 0.35 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... Volts ( Max. area=2.4V- Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition Rev. 0.5 / Aug. 2003 Parameter Max. amplitude=1. Time(ns) Parameter Max. amplitude=1. Time(ns) HY5DV281622DT Specification DDR333 DDR200/266 1.5V 1.5V 1.5V 1. Overshoot V DD Ground Undershoot 6 Specification DDR333 DDR200/266 1.2V 1.2V 1.2V 1. ...
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... HPmin HPmin HPmin - - - QHS QHS CH/L CH/L CH min min min - 0.4 - 0.4 0.9 - 0.9 - 0.9 0.9 - 0.9 - 0.9 HY5DV281622DT Max Min Max Min 100K 8 100K 6 7.0 5.0 7.0 6.0 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.7 -0.7 0.7 -0.75 0.7 -0.7 0.7 -0.75 - 0 ...
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... Signal transitions through the DC region must be monotonic. Rev. 0.5 / Aug. 2003 33 36 Min Max Min Max Min 0.4 0.6 0.4 0.6 0.4 0.4 0.6 0.4 0.6 0.4 0.85 1.15 0.85 1.15 0.85 0.4 - 0.4 - 0.4 0.4 - 0.4 - 0.4 0.9 1.1 0.9 1.1 0.9 0.4 0.6 0.4 0.6 0 1.5 - 1.5 - 1.5 0.4 0.6 0.4 0.6 0 200 - 200 - 200 1tCK 1tCK 1tCK - - + tIS + tIS + tIS - 7.8 - 7.8 - HY5DV281622DT Max Min Max Min Max 0.6 0.4 0.6 0.4 0.6 0.6 0.4 0.6 0.4 0.6 1.15 0.75 1.25 0.75 1.25 - 0 0.5 - 0.5 - 1.1 0.9 1.1 0.9 1.1 0.6 0.4 0.6 0.4 0 1.5 - 1.5 - 0.6 0.4 0.6 0.4 0 200 - 200 - 1tCK 1tCK - - - + tIS + tIS 7.8 - 7.8 - 7.8 Unit Note ...
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... Rev. 0.5 / Aug. 2003 tRFC tRAS tRCDRD HY5DV281622DT tRCDWR tRP tDAL Unit tCK tCK tCK tCK tCK tCK ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 0.5 / Aug. 2003 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50 Ω Zo=50 Ω V REF C =30pF L HY5DV281622DT Symbol Min Max Unit C 2.0 3 2.0 3 4.0 5 ...
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... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 0.5 / Aug. 2003 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) HY5DV281622DT Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) ...